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clk: loongson2: Allow zero divisors for dividers

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LS2K0300 and LS2K0500 ship divider clocks which allows zero divisors,
in which case the divider acts the same as one is specified.

Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to
prepare for future introduction of these clocks.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: maoxiaochuan <maoxiaochuan@loongson.cn>
This commit is contained in:
Yao Zi
2026-02-04 16:39:51 +08:00
committed by maoxiaochuan
parent 1ecbaaf4e7
commit 61bb1eb74b
1 changed files with 2 additions and 1 deletions
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drivers/clk/clk-loongson2.c
+2 -1
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@@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *pdev)
p->parent_name, 0,
clp->base + p->reg_offset,
p->div_shift, p->div_width,
CLK_DIVIDER_ONE_BASED,
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO,
&clp->clk_lock);
break;
case CLK_TYPE_GATE: