liyepan/openloongarch-linux-5.10
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update to 210c2be518

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1. remove unused file and some improvement for pwm and clk
This commit is contained in:
loongson
2024-09-06 11:33:40 +08:00
parent f8d364be6a
commit cad32c3930
5 changed files with 9 additions and 4 deletions
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arch/loongarch/loongson64/init.c
+1 -1
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@@ -258,7 +258,7 @@ static void *get_fdt_by_board_name(void)
#elif defined(CONFIG_LOONGSON_2K300)
if (!strncmp(b_info.board_name, "LS2K300-MINI-DP", 15))
fdt = &__dtb_ls2k300_mini_dp_begin;
if (!strncmp(b_info.board_name, "LS2K300-PAI", 11))
else if (!strncmp(b_info.board_name, "LS2K300-PAI", 11))
fdt = &__dtb_ls2k300_pai_begin;
else
fdt = &__dtb_ls2k300_mini_dp_begin;
drivers/clk/loongson/clk-loongson2k300.c
+3 -3
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@@ -494,7 +494,7 @@ static struct ls2k_clock_desc ls2k_clock_desc_set[CLK_CNT] = {
.clk_ops = &ls2k300_cpu_clk_ops,
#else
.fixed = 1,
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_REFC_SHIFT, .bit_mask = PLL_NODE_0_REFC_MASK}, {.bit_mask = 0}},
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_ODIV_SHIFT, .bit_mask = PLL_NODE_0_ODIV_MASK}, {.bit_mask = 0}},
.freqscale_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_FREQ_SC, .bit_offset = PLL_FREQSCALE_NODE_SHIFT, .bit_mask = PLL_FREQSCALE_NODE_MASK}, {.bit_mask = 0}},
#endif
},
@@ -507,7 +507,7 @@ static struct ls2k_clock_desc ls2k_clock_desc_set[CLK_CNT] = {
.clk_ops = &ls2k300_cpu_clk_ops,
#else
.fixed = 1,
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_REFC_SHIFT, .bit_mask = PLL_NODE_0_REFC_MASK}, {.bit_mask = 0}},
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_ODIV_SHIFT, .bit_mask = PLL_NODE_0_ODIV_MASK}, {.bit_mask = 0}},
.freqscale_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_FREQ_SC, .bit_offset = PLL_FREQSCALE_NODE_SHIFT, .bit_mask = PLL_FREQSCALE_NODE_MASK}, {.bit_mask = 0}},
#endif
},
@@ -520,7 +520,7 @@ static struct ls2k_clock_desc ls2k_clock_desc_set[CLK_CNT] = {
.clk_ops = &ls2k300_cpu_clk_ops,
#else
.fixed = 1,
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_REFC_SHIFT, .bit_mask = PLL_NODE_0_REFC_MASK}, {.bit_mask = 0}},
.div_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_NODE_0_OFFSET, .bit_offset = PLL_NODE_0_ODIV_SHIFT, .bit_mask = PLL_NODE_0_ODIV_MASK}, {.bit_mask = 0}},
.freqscale_reg_set = (struct ls2k_reg_field_desc[]){{.reg_offset = PLL_FREQ_SC, .bit_offset = PLL_FREQSCALE_NODE_SHIFT, .bit_mask = PLL_FREQSCALE_NODE_MASK}, {.bit_mask = 0}},
#endif
},
drivers/net/can/ls_canfd/lscanfd.ko
BIN
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Binary file not shown.
drivers/net/can/ls_canfd/lscanfd_platform.ko
BIN
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Binary file not shown.
drivers/pwm/pwm-ls.c
+5
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@@ -263,6 +263,11 @@ static int ls_pwm_probe(struct platform_device *pdev)
pwm->chip.base = -1;
pwm->chip.npwm = 1;
of_property_read_u32(np, "#pwm-cells", &pwm->chip.of_pwm_n_cells);
// Default of_xlate = of_pwm_simple_xlate
if (pwm->chip.of_pwm_n_cells >= 3)
pwm->chip.of_xlate = of_pwm_xlate_with_flags;
pwm_clock_frequency_get(pdev, np, pwm);
dev_info(&pdev->dev, "pwm->clock_frequency=%llu", pwm->clock_frequency);