up to 833f4f6ce9

arch/loongarch/boot/dts/loongson/Makefile

@@ -1,12 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_LOONGSON64_GENERIC)	+= loongson3_ls7a.dtb
-dtb-$(CONFIG_LOONGSON_2K500)		+= ls2k500_hl_mb.dtb ls2k500_mini_dp.dtb ls2k500_dayu400_mb.dtb ls2k500_modi_hct.dtb ls2k500_zhengtai_pcs1800_v10.dtb \
-										ls2k500_jiaoqian_v10.dtb ls2k500_zjjz.dtb
-dtb-$(CONFIG_LOONGSON_2K1000)		+= ls2k1000_jl_mb.dtb ls2k1000_jl_mb_mu.dtb ls2k1000_jl_mb_nodvo.dtb \
-										ls2k1000_dp.dtb ls2k1000_dp_i2s.dtb ksec_hac_mb.dtb gbkpdm0_v10.dtb gbkpdm0_litong.dtb \
-										ls2k1000_cl_mb.dtb ls2k1000_dp_test.dtb ls2k1000_dp_factory.dtb
-dtb-$(CONFIG_LOONGSON_2P500)		+= ls2p500_evb.dtb ls2p500_rsj_mb_v10.dtb
-
+dtb-$(CONFIG_LOONGSON_2K500)		+= ls2k500_mini_dp.dtb
+dtb-$(CONFIG_LOONGSON_2K1000)		+= ls2k1000_dp.dtb
+dtb-$(CONFIG_LOONGSON_2P500)		+= ls2p500_gbkpjm0_v10.dtb
 dtb-$(CONFIG_LOONGSON_2K300)		+= ls2k300_mini_dp.dtb ls2k300_pai.dtb
 
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))

arch/loongarch/boot/dts/loongson/loongson2k1000.dtsi

@@ -874,7 +874,7 @@
 					};
 
 					cpu_crit: cpu-crit {
-						temperature = <125000>;
+						temperature = <160000>;
 						hysteresis = <5000>;
 						type = "critical";
 					};

arch/loongarch/boot/dts/loongson/loongson2k300.dtsi

@@ -11,6 +11,12 @@
 		serial1 = &uart1;
 		serial2 = &uart2;
 		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
+		serial7 = &uart7;
+		serial8 = &uart8;
+		serial9 = &uart9;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
@@ -93,6 +99,30 @@
 			pinctrl-single,bits = <0x8 0xf0000000 0xf0000000>;
 		};
 
+		uart4_pins: pinmux_G62_G63_as_uart4 {
+			pinctrl-single,bits = <0xc 0xa0000000 0xf0000000>;
+		};
+
+		uart5_pins: pinmux_G64_G65_as_uart5 {
+			pinctrl-single,bits = <0x10 0x000000a 0x0000000f>;
+		};
+
+		uart6_pins: pinmux_G60_G61_as_uart6 {
+			pinctrl-single,bits = <0xc 0x0a000000 0x0f000000>;
+		};
+
+		uart7_pins: pinmux_G68_G69_as_uart7 {
+			pinctrl-single,bits = <0x10 0xf0000a00 0x00000f00>;
+		};
+
+		uart8_pins: pinmux_G70_G71_as_uart8 {
+			pinctrl-single,bits = <0x8 0x0f00a000 0x0f00f000>;
+		};
+
+		uart9_pins: pinmux_G66_G67_as_uart9 {
+			pinctrl-single,bits = <0x10 0x000000a0 0xf00000f0>;
+		};
+
 		i2c0_pins: pinmux_G48_G49_as_i2c0 {
 			pinctrl-single,bits = <0xc 0x0000000f 0x0000000f>;
 		};
@@ -158,6 +188,30 @@
 			pinctrl-single,bits = <0x14 0x00080000 0x000c0000>;
 		};
 
+		tim1_ch1:pinmux_G81_as_tim1_ch1 {
+			pinctrl-single,bits = <0x14 0x0000000c 0x0000000c>;
+		};
+
+		tim1_ch1n:pinmux_G84_as_tim1_ch1n {
+			pinctrl-single,bits = <0x14 0x00000300 0x000000300>;
+		};
+
+		tim1_ch2n:pinmux_G85_as_tim1_ch2n {
+			pinctrl-single,bits = <0x14 0x00000c00 0x000000c00>;
+		};
+
+		tim1_ch3n:pinmux_G86_as_tim1_ch3n {
+			pinctrl-single,bits = <0x14 0x00003000 0x000003000>;
+		};
+
+		tim2_ch1:pinmux_G87_as_tim2_ch1 {
+			pinctrl-single,bits = <0x14 0x0000c000 0x00000c000>;
+		};
+
+		tim2_ch2:pinmux_G88_as_tim2_ch2 {
+			pinctrl-single,bits = <0x14 0x00030000 0x00030000>;
+		};
+
 		sdio0_pins: pinmux_G90_G99_as_sdio {
 			pinctrl-single,bits = <0x14 0xfff00000 0xfff00000
 						0x18 0x000000ff 0x000000ff>;
@@ -244,6 +298,78 @@
 			status = "disabled";
 		};
 
+		uart4: serial@0x16101000 {
+			compatible = "ns16550a";
+			reg = <0 0x16101000 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <2>;
+			pinctrl-0 = <&uart4_pins>;
+			pinctrl-names = "default";
+			no-loopback-test;
+		};
+
+		uart5: serial@0x16101400 {
+			compatible = "ns16550a";
+			reg = <0 0x16101400 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <2>;
+			no-loopback-test;
+			pinctrl-0 = <&uart5_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		uart6: serial@0x16101800 {
+			compatible = "ns16550a";
+			reg = <0 0x16101800 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <3>;
+			no-loopback-test;
+			pinctrl-0 = <&uart6_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		uart7: serial@0x16101c00 {
+			compatible = "ns16550a";
+			reg = <0 0x16101c00 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <3>;
+			no-loopback-test;
+			pinctrl-0 = <&uart7_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		uart8: serial@0x16102000 {
+			compatible = "ns16550a";
+			reg = <0 0x16102000 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <3>;
+			no-loopback-test;
+			pinctrl-0 = <&uart8_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		uart9: serial@0x16102400 {
+			compatible = "ns16550a";
+			reg = <0 0x16102400 0 0x10>;
+			clock-frequency = <200000000>;
+			interrupt-parent = <&icu>;
+			interrupts = <3>;
+			no-loopback-test;
+			pinctrl-0 = <&uart9_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+
 		dc: dc@0x16090000 {
 			compatible = "loongson,ls2k0300-dc";
 			reg = <0 0x16090000 0 0x00010000>;
@@ -267,8 +393,11 @@
 		};
 
 		wdt: syscon@0x16124000 {
-			compatible = "syscon";
-			reg = <0x0 0x16124000 0x0 0xc>;
+			compatible = "loongson,ls2x-wdt", "syscon";
+			reg = <0 0x16124000 0 0xC>;
+			clocks = <&clocks CLK_APB>;
+			clock-names = "wdt-clk";
+			status = "okay";
 		};
 
 		reboot {

arch/loongarch/boot/dts/loongson/loongson2p500.dtsi

@@ -22,6 +22,8 @@
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
+		mmc0 = &emmc0;
+		mmc1 = &sdio1;
 	};
 
 	// memory {
@@ -82,7 +84,6 @@
 		interrupts = <4>;
 	};
 
-#if 1
 	extioiic: interrupt-controller@0x14001600 {
 		compatible = "loongson,extioi-interrupt-controller";
 		interrupt-controller;
@@ -94,7 +95,6 @@
 		misc_func=<0x100>;
 		eio_en_off=<15>;
 	};
-#endif
 
 	// uart0 uart1 分线复用
 	pinmux_uart: pinmux@14000100 {
@@ -156,6 +156,10 @@
 			pinctrl-single,bits = <0x0 0xff000000 0xff000000>;
 		};
 
+		g12_15_as_gpio: pinmux_g12_15_as_gpio {
+			pinctrl-single,bits = <0x0 0x00000000 0xff000000>;
+		};
+
 		//sdio0 gpio4~7 2
 		//      gpio16~21 3
 		sdio0_pins: pinmux_i2c0_pins {
@@ -457,13 +461,18 @@
 			status = "disabled";
 		};
 
+		// EMMC 与 SDIO 必须同时使用扩展中断，
+		// 如果只有SDIO使用扩展中断，则中断不会响应
+		// 表现为系统卡死
 		/*emmc*/
-		emmc0@0x14210000 {
+		emmc0: mmc0@0x14210000 {
 			#address-cells = <2>;
 			compatible = "loongson,ls2k_sdio_1.1";
 			reg = <0 0x14210000 0 0x1000>;
-			interrupt-parent = <&icu>;
-			interrupts = <13>;
+			//interrupt-parent = <&icu>;
+			//interrupts = <13>;
+			interrupt-parent = <&extioiic>;
+			interrupts = <8>;
 			interrupt-names = "ls2k_mci_irq";
 			dma-mask = <0xffffffff 0xffffffff>;
 			clock-frequency = <0 200000000>;
@@ -473,25 +482,27 @@
 			no-sdio;
 			pinctrl-0 = <&sdio0_pins>;
 			pinctrl-names = "default";
+			status = "disabled";
 		};
-#if 0
-        sdio:sdio0@0x14218000 {
+
+		sdio1: mmc1@0x14218000 {
 			#address-cells = <2>;
-			compatible = "loongson,ls2k_sdio_1.1";
+			compatible = "loongson,ls2k_sdio_1.2";
 			reg = <0 0x14218000 0 0x1000>;
-			interrupt-parent = <&extioiic>;
-			interrupts = <10>;
-			interrupt-names = "ls2k_mci_irq";
+			interrupt-parent = <&icu>;
+			interrupts = <13>;
+			//interrupt-parent = <&extioiic>;
+			//interrupts = <10>;
+			interrupt-names = "ls2k_sdio_irq";
 			clock-frequency = <0 200000000>;
 			dma-mask = <0xffffffff 0xffffffff>;
 			bus-width = <4>;
 			cap-sd-highspeed;
-			no-mmc;
-			pinctrl-0 = <&sdio1_pins>;
-			pinctrl-names = "default";
+			cap-mmc-highspeed;
+			//no-mmc;
 			status = "disabled";
 		};
-#endif
+
 		gmac0: ethernet@0x14140000 {
 			compatible = "snps,dwmac-3.70a";
 			reg = <0 0x14140000 0 0x10000>;
@@ -526,7 +537,7 @@
 			status = "disabled";
 		};
 
-		otg@0x14100000 {
+		otg: otg@0x14100000 {
 			//compatible = "loongson,dwc-otg","dwc-otg","loongson,dwc2";
 			compatible = "loongson,loongson2-dwc2";
 			reg = <0 0x14100000 0 0x40000>;

arch/loongarch/boot/dts/loongson/ls2k300_g2k03z0_core_v10.dtsi

@@ -11,12 +11,13 @@
 		bootargs = "earlycon";
 	};
 
-	memory {
-		name = "memory";
-		device_type = "memory";
-		reg =  <0 0x00200000 0 0x0ee00000
-			0 0x90000000 0 0x10000000>;
-	};
+	/* not need memory node, we get memory info from boot params. */
+	//memory {
+	//	name = "memory";
+	//	device_type = "memory";
+	//	reg =  <0 0x00200000 0 0x0ee00000
+	//		0 0x90000000 0 0x10000000>;
+	//};
 
 	reserved-memory {
 		#address-cells = <2>;

arch/loongarch/boot/dts/loongson/ls2k300_mini_dp.dts

@@ -27,7 +27,7 @@
 		/* lcd power on control gpio */
 		// enable-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>;
 		// power-supply = <&vdd_lcd>;
-#if 1	// 4.3' LCD
+#if 0	// 4.3' LCD
 		width-mm = <223>;
 		height-mm = <125>;
 		label = "ATK-MD0430R-800x480";
@@ -107,6 +107,10 @@
 &i2c1 {
 	status = "ok"
 
+	// 两款芯片不能同时支持，因为用同一个GPIO
+	// 但可以在两个屏幕间切换
+
+	// 4.3寸触屏芯片
 	touchpad: gt9147@14 {
 		compatible = "goodix,gt9147";
 		reg = <0x14>;
@@ -116,6 +120,15 @@
 		interrupts = <210 IRQ_TYPE_EDGE_FALLING>;
 		irq-gpios = <&gpio 82 GPIO_ACTIVE_LOW>;
 	};
+
+	// 7寸触屏芯片
+	touchpad_1: gt911@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		interrupt-parent = <&gpio>;
+		interrupts = <210 IRQ_TYPE_EDGE_FALLING>;
+		irq-gpios = <&gpio 82 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &i2c2 {

arch/loongarch/boot/dts/loongson/ls2k300_pai.dts

@@ -14,12 +14,13 @@
 		bootargs = "earlycon";
 	};
 
-	memory {
-		name = "memory";
-		device_type = "memory";
-		reg =  <0 0x00200000 0 0x0ee00000
-			0 0x90000000 0 0x10000000>;
-	};
+	/* not need memory node, we get memory info from boot params. */
+	//memory {
+	//	name = "memory";
+	//	device_type = "memory";
+	//	reg =  <0 0x00200000 0 0x0ee00000
+	//		0 0x90000000 0 0x10000000>;
+	//};
 
 	reserved-memory {
 		#address-cells = <2>;
@@ -45,16 +46,22 @@
 		};
 	};
 
+	lcd_backlight: backlight {
+		compatible = "gpio-backlight";
+		gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
 	panel: dvo-connector@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "panel-lvds", "auo,b101ean01";
-		//backlight = <&lcd_backlight>;
+		backlight = <&lcd_backlight>;
 
 		/* lcd power on control gpio */
 		// enable-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>;
 		// power-supply = <&vdd_lcd>;
-#if 1	// 4.3' LCD
+#if 0	// 4.3' LCD
 		width-mm = <223>;
 		height-mm = <125>;
 		label = "ATK-MD0430R-800x480";
@@ -141,6 +148,26 @@
 	status = "okay";
 };
 
+&uart2 {
+	status = "ok"
+};
+
+&uart5 {
+	status = "disabled";
+};
+
+&uart6 {
+	status = "disabled";
+};
+
+&uart7 {
+	status = "disabled";
+};
+
+&uart8 {
+	status = "disabled";
+};
+
 &spi0 {
 	status = "okay";
 
@@ -151,6 +178,20 @@
 	};
 };
 
+&spi1 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "ok"
+
+	mcp3004@0 {
+		compatible = "mcp3004";
+		reg = <0>;
+		spi-max-frequency = <1500000>;
+	};
+};
+
 &gmac0 {
 	status = "okay";
 	phy-handle = <&yt8511h0>;
@@ -188,6 +229,25 @@
 &i2c0 {
 	status = "ok"
 
+	touchpad: gt9147@14 {
+		compatible = "goodix,gt9147";
+		reg = <0x14>;
+		// 2K300 GPIO 支持中断控制
+		// GPIO 中断号为 vhwirq-base + pinnum (170 = 128 + 42)
+		interrupt-parent = <&gpio>;
+		interrupts = <170 IRQ_TYPE_EDGE_FALLING>;
+		irq-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio 55 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c1 {
+	status = "ok"
+};
+
+&i2c2 {
+	status = "okay";
+
 	codec: es8388@11{
 		compatible = "everest,es8388";
 		reg = <0x11>;
@@ -197,65 +257,23 @@
 		PVDD-supply = <&vccio_codec>;
 		clocks = <&es8388_clk 0>;
 	};
-
-	touchpad: gt9147@14 {
-		compatible = "goodix,gt9147";
-		reg = <0x14>;
-		// 2K300 GPIO 支持中断控制
-		// 暂时PCB布局有问题，所以随便写个引脚
-		// GPIO 中断号为 vhwirq-base + pinnum (181 = 128 + 53)
-		interrupt-parent = <&gpio>;
-		interrupts = <181 IRQ_TYPE_EDGE_FALLING>;
-		irq-gpios = <&gpio 53 GPIO_ACTIVE_LOW>;
-	};
 };
 
-&i2c1 {
-	status = "ok"
+
+&can0 {
+	status = "disabled";
 };
 
-// &i2c2 {
-// 	status = "okay";
-// };
-
-&uart2 {
-	status = "ok"
+&can1 {
+	status = "disabled";
 };
 
-// &can0 {
-// 	status = "okay";
-// };
+&can2 {
+	status = "disabled";
+};
 
-// &can1 {
-// 	status = "okay";
-// };
-
-// &can2 {
-// 	status = "okay";
-// };
-
-// &can3 {
-// 	status = "okay";
-// };
-
-// &spi1 {
-// 	status = "okay";
-
-// 	spidev0@0 {
-// 		compatible = "rohm,dh2228fv";
-// 		reg = <0>;
-// 		spi-max-frequency = <50000000>;
-// 	};
-// };
-
-&spi2 {
-	status = "ok"
-
-	mcp3004@0 {
-		compatible = "mcp3004";
-		reg = <0>;
-		spi-max-frequency = <1500000>;
-	};
+&can3 {
+	status = "disabled";
 };
 
 &adc {
@@ -287,3 +305,7 @@
 &sound {
 	status = "okay";
 };
+
+&pwm0 {
+	status = "okay";
+};

arch/loongarch/boot/dts/loongson/ls2p500_g2p05z0_v10.dtsi

@@ -45,3 +45,7 @@
 	};
 };
 
+&emmc0 {
+	status = "okay";
+};
+

arch/loongarch/boot/dts/loongson/ls2p500_gbkpjm0_v10.dts

@@ -0,0 +1,61 @@
+#include "ls2p500_g2p05z0_v10.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "LS2P500-GBKPJM0";
+};
+
+// UART LCD
+&uart1 {
+	status = "okay";
+};
+
+// PRT-UART0
+&uart4 {
+	status = "okay";
+};
+
+// SCA-UART0
+&uart6 {
+	status = "okay";
+};
+
+// PRT-I2C0
+&i2c2 {
+	status = "okay";
+};
+
+// PRT-I2C1
+&i2c3 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+};
+
+&spi3 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+&otg {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&sdio1 {
+	status = "okay";
+	pinctrl-0 = <&sdio1_pins>, <&g12_15_as_gpio>;
+	pinctrl-names = "default";
+	cd-gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
+};

arch/loongarch/configs/loongson_2k300_defconfig

@@ -202,8 +202,6 @@ CONFIG_NETLINK_DIAG=y
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_CAN=y
-#CONFIG_CAN_LSCAN=y
-#CONFIG_CAN_LSCAN_PLATFORM=y
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_RFKILL=y
@@ -321,17 +319,42 @@ CONFIG_PPP_SYNC_TTY=y
 # CONFIG_WLAN_VENDOR_MARVELL is not set
 # CONFIG_WLAN_VENDOR_MEDIATEK is not set
 # CONFIG_WLAN_VENDOR_MICROCHIP is not set
-# CONFIG_WLAN_VENDOR_RALINK is not set
+CONFIG_RT2X00=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT61PCI=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2X00_DEBUG=y
+CONFIG_RTL8180=m
 CONFIG_RTL8187=m
 CONFIG_RTL_CARDS=m
 CONFIG_RTL8192CE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
 CONFIG_RTL8188EE=m
 CONFIG_RTL8192EE=m
+CONFIG_RTL8821AE=m
 CONFIG_RTL8192CU=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
 CONFIG_RTW88=m
+CONFIG_RTW88_8822BE=m
 CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
 CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_8723DE=m
 CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821CU=m
 # CONFIG_WLAN_VENDOR_RSI is not set
 # CONFIG_WLAN_VENDOR_ST is not set
 # CONFIG_WLAN_VENDOR_TI is not set

arch/loongarch/configs/loongson_2p500_defconfig

@@ -82,6 +82,169 @@ CONFIG_INET_DIAG=m
 CONFIG_INET_UDP_DIAG=m
 # CONFIG_IPV6 is not set
 CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_LOG_NETDEV=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_SNMP=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_CT_NETLINK_TIMEOUT=y
+CONFIG_NF_CT_NETLINK_HELPER=y
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=y
+CONFIG_NFT_CT=y
+CONFIG_NFT_COUNTER=y
+CONFIG_NFT_CONNLIMIT=y
+CONFIG_NFT_LOG=y
+CONFIG_NFT_LIMIT=y
+CONFIG_NFT_MASQ=y
+CONFIG_NFT_REDIR=y
+CONFIG_NFT_TUNNEL=y
+CONFIG_NFT_OBJREF=y
+CONFIG_NFT_QUEUE=y
+CONFIG_NFT_QUOTA=y
+CONFIG_NFT_REJECT=y
+CONFIG_NFT_HASH=y
+CONFIG_NFT_XFRM=y
+CONFIG_NFT_SOCKET=y
+CONFIG_NFT_OSF=y
+CONFIG_NFT_TPROXY=y
+CONFIG_NFT_SYNPROXY=y
+CONFIG_NFT_DUP_NETDEV=y
+CONFIG_NFT_FWD_NETDEV=y
+CONFIG_NF_FLOW_TABLE=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_HMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LED=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_CGROUP=y
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_L2TP=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NETFILTER_XT_MATCH_OSF=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_RECENT=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_SET=y
+CONFIG_IP_SET_BITMAP_IP=y
+CONFIG_IP_SET_BITMAP_IPMAC=y
+CONFIG_IP_SET_BITMAP_PORT=y
+CONFIG_IP_SET_HASH_IP=y
+CONFIG_IP_SET_HASH_IPMARK=y
+CONFIG_IP_SET_HASH_IPPORT=y
+CONFIG_IP_SET_HASH_IPPORTIP=y
+CONFIG_IP_SET_HASH_IPPORTNET=y
+CONFIG_IP_SET_HASH_IPMAC=y
+CONFIG_IP_SET_HASH_MAC=y
+CONFIG_IP_SET_HASH_NETPORTNET=y
+CONFIG_IP_SET_HASH_NET=y
+CONFIG_IP_SET_HASH_NETNET=y
+CONFIG_IP_SET_HASH_NETPORT=y
+CONFIG_IP_SET_HASH_NETIFACE=y
+CONFIG_IP_SET_LIST_SET=y
+CONFIG_IP_VS=y
+CONFIG_IP_VS_DEBUG=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_RR=y
+CONFIG_IP_VS_WRR=y
+CONFIG_IP_VS_LC=y
+CONFIG_IP_VS_WLC=y
+CONFIG_IP_VS_FO=y
+CONFIG_IP_VS_OVF=y
+CONFIG_IP_VS_LBLC=y
+CONFIG_IP_VS_LBLCR=y
+CONFIG_IP_VS_DH=y
+CONFIG_IP_VS_SH=y
+CONFIG_IP_VS_MH=y
+CONFIG_IP_VS_SED=y
+CONFIG_IP_VS_NQ=y
+CONFIG_IP_VS_FTP=y
+CONFIG_IP_VS_PE_SIP=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_DUP_IPV4=y
+CONFIG_NFT_FIB_IPV4=y
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_FLOW_TABLE_IPV4=y
+CONFIG_NF_LOG_ARP=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_SYNPROXY=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_BRIDGE=y
 CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_CAN=m
@@ -261,6 +424,9 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_XR21V141X=y
 CONFIG_USB_GADGET=y
 CONFIG_MMC=y
 CONFIG_MMC_LS2K=y

arch/loongarch/include/asm/mach-loongson64/boot_param.h

@@ -106,11 +106,8 @@ struct loongson_system_configuration {
 extern void *loongson_fdt_blob;
 extern u32 __dtb_loongson3_ls7a_begin[];
 extern u32 __dtb_ls2k500_mini_dp_begin[];
-extern u32 __dtb_ls2k500_dayu400_mb_begin[];
-extern u32 __dtb_ls2k1000_jl_mb_begin[];
 extern u32 __dtb_ls2k1000_dp_begin[];
-extern u32 __dtb_ls2p500_evb_begin[];
-extern u32 __dtb_ls2p500_rsj_mb_v10_begin[];
+extern u32 __dtb_ls2p500_gbkpjm0_v10_begin[];
 extern u32 __dtb_ls2k300_mini_dp_begin[];
 extern u32 __dtb_ls2k300_pai_begin[];
 extern char __dtb_start[];

arch/loongarch/loongson64/Kconfig

@@ -74,7 +74,6 @@ config LOONGSON_2K300
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select ZONE_DMA32
 	select USE_OF
-	select LOONGSON_MEM_MAP_NEED_FIX
 	select COMMON_CLK
 	help
 	  Loongson 2K300 family SoC.

arch/loongarch/loongson64/init.c

@@ -228,17 +228,14 @@ static inline int check_cpu_full_name_invaild(int cpu)
 		return 0;
 }
 
-static void *get_fdt(void)
+static void *get_fdt_by_board_name(void)
 {
 	void *fdt = NULL;
-
 	if (b_info.board_name) {
 #ifdef CONFIG_LOONGSON_2K500
 		int i;
 		if (!strncmp(b_info.board_name, "LS2K500-MINI-DP", 15))
 			fdt = &__dtb_ls2k500_mini_dp_begin;
-		else if (!strncmp(b_info.board_name, "LS2K500-DAYU400-MB", 17))
-			fdt = &__dtb_ls2k500_dayu400_mb_begin;
 		else
 			fdt = &__dtb_ls2k500_mini_dp_begin;
 
@@ -254,12 +251,10 @@ static void *get_fdt(void)
 			fdt = &__dtb_ls2k1000_dp_begin;
 		}
 #elif defined(CONFIG_LOONGSON_2P500)
-		if (!strncmp(b_info.board_name, "LS2P500-EVB", 11))
-			fdt = &__dtb_ls2p500_evb_begin;
-		else if (!strncmp(b_info.board_name, "LS2P500-RSJ", 11))
-			fdt = &__dtb_ls2p500_rsj_mb_v10_begin;
+		if (!strncmp(b_info.board_name, "LS2P500-GBKPJM0", 15))
+			fdt = &__dtb_ls2p500_gbkpjm0_v10_begin;
 		else
-			fdt = &__dtb_ls2p500_evb_begin;
+			fdt = &__dtb_ls2p500_gbkpjm0_v10_begin;
 #elif defined(CONFIG_LOONGSON_2K300)
 		if (!strncmp(b_info.board_name, "LS2K300-MINI-DP", 15))
 			fdt = &__dtb_ls2k300_mini_dp_begin;
@@ -269,6 +264,23 @@ static void *get_fdt(void)
 			fdt = &__dtb_ls2k300_mini_dp_begin;
 #endif
 	}
+	return fdt;
+}
+
+static void *get_fdt(void)
+{
+	void *fdt = NULL;
+
+	if (fw_passed_dtb)
+		fdt = (void *)fw_passed_dtb;
+	else if (fw_arg3) {
+		// uboot的传参基本在这个判断
+		if (!fdt_check_header((void *)fw_arg3))
+			fdt = (void *)fw_arg3;
+	}
+
+	if (!fdt)
+		fdt = get_fdt_by_board_name();
 
 	if (!fdt && IS_ENABLED(CONFIG_BUILTIN_DTB)
 			&& (&__dtb_start != &__dtb_end))

drivers/gpio/gpio-loongson-irq.c

@@ -55,7 +55,7 @@
 	writeb(val, self->reg + REG_GPIO_IRQCLR(self) + p)
 #define lsirq_gpio_get_reg_irqsta(self, p) \
 	readb(self->reg + REG_GPIO_IRQSTA(self) + p)
-#define lsirq_gpio_get_reg_irqdul(self, p, val) \
+#define lsirq_gpio_set_reg_irqdul(self, p, val) \
 	writeb(val, self->reg + REG_GPIO_IRQDUL(self) + p)
 
 typedef struct lsirq_gpio_regtable_s {
@@ -241,29 +241,30 @@ static int mthd_lsirq_gpio_irqsettype(struct irq_data *d, u32 type)
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		lsirq_gpio_set_reg_irq(priv, pin, 1);
-		lsirq_gpio_get_reg_irqdul(priv, pin, 0);
+		lsirq_gpio_set_reg_irqdul(priv, pin, 0);
 		lsirq_gpio_set_reg_irqpol(priv, pin, 1);
 		lsirq_gpio_set_reg_irqedg(priv, pin, 1);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
 		lsirq_gpio_set_reg_irq(priv, pin, 1);
-		lsirq_gpio_get_reg_irqdul(priv, pin, 0);
+		lsirq_gpio_set_reg_irqdul(priv, pin, 0);
 		lsirq_gpio_set_reg_irqpol(priv, pin, 0);
 		lsirq_gpio_set_reg_irqedg(priv, pin, 1);
 		break;
 	case IRQ_TYPE_EDGE_BOTH:
 		lsirq_gpio_set_reg_irq(priv, pin, 1);
-		lsirq_gpio_get_reg_irqdul(priv, pin, 1);
+		lsirq_gpio_set_reg_irqdul(priv, pin, 1);
+		lsirq_gpio_set_reg_irqedg(priv, pin, 1);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
 		lsirq_gpio_set_reg_irq(priv, pin, 1);
-		lsirq_gpio_get_reg_irqdul(priv, pin, 0);
+		lsirq_gpio_set_reg_irqdul(priv, pin, 0);
 		lsirq_gpio_set_reg_irqpol(priv, pin, 0);
 		lsirq_gpio_set_reg_irqedg(priv, pin, 0);
 		break;
 	case IRQ_TYPE_LEVEL_HIGH:
 		lsirq_gpio_set_reg_irq(priv, pin, 1);
-		lsirq_gpio_get_reg_irqdul(priv, pin, 0);
+		lsirq_gpio_set_reg_irqdul(priv, pin, 0);
 		lsirq_gpio_set_reg_irqpol(priv, pin, 1);
 		lsirq_gpio_set_reg_irqedg(priv, pin, 0);
 		break;

drivers/gpu/drm/loongson/lsdc_pll.c

@@ -104,7 +104,7 @@ union lsdc_pixpll_bitmap {
 	struct ls7a1000_pixpll_bitmap ls7a1000;
 	struct ls2k1000_pixpll_bitmap ls2k1000;
 	struct ls2k0500_pixpll_bitmap ls2k0500;
-	struct ls2k0500_pixpll_bitmap ls2k0300;
+	struct ls2k0300_pixpll_bitmap ls2k0300;
 
 	u32 dword[4];
 };
@@ -128,6 +128,51 @@ struct pixclk_to_pll_parm {
  * Pixel clock to PLL parameters translation table.
  * Small static cached value to speed up PLL parameters calculation.
  */
+#ifdef CONFIG_LOONGSON_2K300
+static const struct pixclk_to_pll_parm pll_param_table[] = {
+	{148500, 1920, 1080, 60,  16,  99, 5},	/* 1920x1080@60Hz */
+						/* 1920x1080@50Hz */
+	{174500, 1920, 1080, 75,  11,  48, 3},	/* 1920x1080@75Hz */
+	{181250, 2560, 1080, 75,   9,  68, 5},	/* 2560x1080@75Hz */
+	{297000, 2560, 1080, 30,   8,  99, 5},	/* 3840x2160@30Hz */
+	{301992, 1920, 1080, 100, 12, 151, 5},	/* 1920x1080@100Hz */
+	{146250, 1680, 1050, 60,  16,  78, 4},	/* 1680x1050@60Hz */
+	{135000, 1280, 1024, 75,  12,  54, 4},	/* 1280x1024@75Hz */
+	{119000, 1680, 1050, 60,  24, 119, 5},	/* 1680x1050@60Hz */
+	{108000, 1600, 900,  60,  14,  63, 5},	/* 1600x900@60Hz  */
+						/* 1280x1024@60Hz */
+						/* 1280x960@60Hz */
+						/* 1152x864@75Hz */
+
+	{106500, 1440, 900,  60,  16,  71, 5},	/* 1440x900@60Hz */
+	{88750,  1440, 900,  60,  24,  71, 4},	/* 1440x900@60Hz */
+	{83500,  1280, 800,  60,  23,  48, 3},	/* 1280x800@60Hz */
+	{71000,  1280, 800,  60,  24,  71, 5},	/* 1280x800@60Hz */
+
+	{74250,  1280, 720,  60,  32,  99, 5},	/* 1280x720@60Hz */
+						/* 1280x720@50Hz */
+
+	{78750,  1024, 768,  75,  24,  63, 4},	/* 1024x768@75Hz */
+	{75000,  1024, 768,  70,  20,  50, 4},	/* 1024x768@70Hz */
+	{65000,  1024, 768,  60,  24,  39, 3},	/* 1024x768@60Hz */
+
+	{51200,  1024, 600,  60,  30,  64, 5},	/* 1024x600@60Hz */
+
+	{57284,  832,  624,  75,  31,  74, 5},	/* 832x624@75Hz */
+	{49500,  800,  600,  75,  32,  66, 5},	/* 800x600@75Hz */
+	{50000,  800,  600,  72,  30,  50, 4},	/* 800x600@72Hz */
+	{40000,  800,  600,  60,  36,  36, 3},	/* 800x600@60Hz */
+	{36000,  800,  600,  56,  40,  36, 3},	/* 800x600@56Hz */
+	{31500,  640,  480,  75,  48,  63, 5},	/* 640x480@75Hz */
+						/* 640x480@73Hz */
+
+	{30240,  640,  480,  67,  50,  63, 5},	/* 640x480@67Hz */
+	{27000,  720,  576,  50,  56,  63, 5},	/* 720x576@60Hz */
+	{25175,  640,  480,  60,  61,  64, 5},	/* 640x480@60Hz */
+	{25200,  640,  480,  60,  60,  63, 5},	/* 640x480@60Hz */
+						/* 720x480@60Hz */
+};
+#else
 static const struct pixclk_to_pll_parm pll_param_table[] = {
 	{148500, 1920, 1080, 60, 11, 49,  3},   /* 1920x1080@60Hz */
 						/* 1920x1080@50Hz */
@@ -169,7 +214,7 @@ static const struct pixclk_to_pll_parm pll_param_table[] = {
 	{25200,  640,  480,  60, 50, 63,  5},   /* 640x480@60Hz */
 						/* 720x480@60Hz */
 };
-
+#endif
 /**
  * lsdc_pixpll_setup - ioremap the device dependent PLL registers
  *
@@ -197,6 +242,7 @@ static bool lsdc_pixpll_find(struct lsdc_pll * const this,
 			     unsigned int clock,
 			     struct lsdc_pll_core_values * const pout)
 {
+	struct pixclk_to_pll_parm* para = pll_param_table;
 	unsigned int num = ARRAY_SIZE(pll_param_table);
 	unsigned int i;
 
@@ -484,45 +530,45 @@ static int ls2k0300_pixpll_param_update(struct lsdc_pll * const this,
 	bool locked;
 
 	/* set sel_pll_out0 0 */
-	val = readw(reg);
+	val = readl(reg);
 	val &= ~(1UL << 0);
-	writew(val, reg);
+	writel(val, reg);
 
 	/* bypass */
 	val |= (1UL << 4);
 
 	/* allow software setting the PLL */
 	val |= (1UL << 3);
-	writew(val, reg);
+	writel(val, reg);
 
 	/* pll powerdown */
-	val = readw(reg);
+	val = readl(reg);
 	val |= (1UL << 5);
-	writew(val, reg);
+	writel(val, reg);
 
 	/* Update the pll params */
 	val = (param->div_out << 24) |
 	      (param->loopc << 15) |
 	      (param->div_ref << 8);
 
-	writew(val, reg);
+	writel(val, reg);
 	/* unbypass */
 	val &= ~(1UL << 4);
 	/* power up */
 	val &= ~(1UL << 5);
 
-	writew(val, reg);
+	writel(val, reg);
 
 	/* wait pll setup and locked */
 	do {
-		val = readw(reg);
+		val = readl(reg);
 		locked = val & 0x80;
 		counter++;
 	} while (locked == false);
 
 	DRM_DEBUG_DRIVER("%u loop waited\n", counter);
 	/* select PIX0 */
-	writew((val | 1), reg);
+	writel((val | 1), reg);
 
 	return 0;
 }
@@ -571,13 +617,22 @@ static unsigned int lsdc_get_clock_rate(struct lsdc_pll * const this,
 			pout->loopc = obj->loopc;
 			pout->div_out = obj->div_out;
 		}
-	} else if (desc->chip == LSDC_CHIP_2K0500 || desc->chip == LSDC_CHIP_2K0300) {
+	} else if (desc->chip == LSDC_CHIP_2K0500) {
 		struct ls2k0500_pixpll_bitmap *obj;
 
-		if (desc->chip == LSDC_CHIP_2K0300)
-			obj = &parms.ls2k0300;
-		else
-			obj = &parms.ls2k0500;
+		obj = &parms.ls2k0500;
+
+		parms.dword[0] = readl(this->mmio);
+		out = this->ref_clock / obj->div_ref * obj->loopc / obj->div_out;
+		if (pout) {
+			pout->div_ref = obj->div_ref;
+			pout->loopc = obj->loopc;
+			pout->div_out = obj->div_out;
+		}
+	} else if (desc->chip == LSDC_CHIP_2K0300) {
+		struct ls2k0300_pixpll_bitmap *obj;
+
+		obj = &parms.ls2k0300;
 
 		parms.dword[0] = readl(this->mmio);
 		out = this->ref_clock / obj->div_ref * obj->loopc / obj->div_out;

drivers/gpu/drm/loongson/lsdc_regs.h

@@ -17,8 +17,11 @@
 /*
  * PIXEL PLL
  */
+#ifdef CONFIG_LOONGSON_2K300
+#define LSDC_PLL_REF_CLK                120000           /* kHz */
+#else
 #define LSDC_PLL_REF_CLK                100000           /* kHz */
-
+#endif
 /*
  * Those PLL registers are not located at DC reg bar space,
  * there are relative to LSXXXXX_CFG_REG_BASE.

drivers/i2c/busses/i2c-lsfs.c

@@ -242,11 +242,11 @@ static void ls_i2c_handle_read(struct ls_i2c_dev *i2c_dev, int flag)
 		complete(&i2c_dev->complete);
 		break;
 	case 3:
-		if (readl(i2c_dev->base + I2C_CR2) & I2C_CR2_ITBUFEN) {
-			i2c_clr_bits(reg, I2C_CR2_ITBUFEN);
+		i2c_clr_bits(reg, I2C_CR2_ITBUFEN);
+		// 必须 delay 至少 100us
+		udelay(500);
+		if (flag != 1)
 			break;
-		}
-
 		reg = i2c_dev->base + I2C_CR1;
 		i2c_clr_bits(reg, I2C_CR1_ACK);
 	default:

drivers/input/touchscreen/goodix.c

@@ -988,8 +988,11 @@ static void goodix_read_config(struct goodix_ts_data *ts)
 		ts->max_touch_num = GOODIX_MAX_CONTACTS;
 		return;
 	}
-
+#ifndef CONFIG_LOONGSON_2K300
+	// 2K300 触屏有时候配置会读成高电平触发，造成触屏用不了
+	// 所以在 2K300 上就直接用默认的下降沿触发，临时解决
 	ts->int_trigger_type = ts->config[TRIGGER_LOC] & 0x03;
+#endif
 	ts->max_touch_num = ts->config[MAX_CONTACTS_LOC] & 0x0f;
 
 	x_max = get_unaligned_le16(&ts->config[RESOLUTION_LOC]);

drivers/mmc/host/ls2kmci.c

@@ -334,7 +334,10 @@ static void ls2k_cmd_data_fix(struct ls2k_mci_host *host,
 	int i, j;
 	u32 *data;
 
-	if (host->app_cmd != SD_APP_SEND_SCR &&
+	if (host->pdata->version == LOONGSON_SDIO_EMMC_VER_1_2) {
+		if (cmd->opcode != SD_SWITCH)
+			return;
+	} else if (host->app_cmd != SD_APP_SEND_SCR &&
 		host->app_cmd != SD_APP_SEND_NUM_WR_BLKS &&
 		host->app_cmd != SD_APP_SD_STATUS &&
 		cmd->opcode != MMC_SEND_WRITE_PROT &&
@@ -360,12 +363,22 @@ static irqreturn_t ls2k_mci_irq(int irq, void *dev_id)
 {
 	struct ls2k_mci_host *host = dev_id;
 	struct mmc_command *cmd;
-	u32 mci_csta, mci_dsta, mci_imsk;
+	u32 mci_csta, mci_dsta, mci_imsk, mci_dclear;
 
 	mci_csta = readl(host->base + SDICMDSTA);
 	mci_imsk = readl(host->base + SDIINTMSK);
 	mci_dsta = readl(host->base + SDIDSTA);
 
+	if (mci_dsta & SDIDSTA_SDIOIRQDETECT) {
+		if (mci_imsk & SDIIMSK_SDIOIRQ) {
+			mci_dclear = SDIIMSK_SDIOIRQ;
+			writel(mci_dclear, host->base + SDIINTMSK);
+
+			mmc_signal_sdio_irq(host->mmc);
+			return IRQ_HANDLED;
+		}
+	}
+
 	if ((host->complete_what == COMPLETION_NONE) ||
 	    (host->complete_what == COMPLETION_FINALIZE)) {
 		host->status = "nothing to complete";
@@ -688,7 +701,7 @@ static void ls2k_mci_send_request(struct mmc_host *mmc)
 			}
 	}
 
-	if (cmd->opcode == 0x19) {
+	if ((cmd->opcode == MMC_WRITE_BLOCK) || (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)) {
 		retry_n = 1000;
 		while (retry_n--) {
 			if ((readl(host->base + 0x2c) & (0x1 << 14)) &&
@@ -701,7 +714,6 @@ static void ls2k_mci_send_request(struct mmc_host *mmc)
 			dbg(host, dbg_err, "may losing int when tx fifo is not full\n");
 	}
 
-
 	/* Send command */
 	ls2k_mci_send_command(host, cmd);
 
@@ -811,11 +823,30 @@ int ls2k_mci_gpio_get_cd(struct mmc_host *host)
 	return value;
 }
 
+static void ls2k_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct ls2k_mci_host *host = mmc_priv(mmc);
+	u32 val;
+
+	if (enable) {
+		val = readl(host->base + SDIINTEN);
+		val |= SDIIMSK_SDIOIRQ;
+		writel(val, host->base + SDIINTEN);
+	} else {
+		val = readl(host->base + SDIINTEN);
+		val &= ~SDIIMSK_SDIOIRQ;
+		writel(val, host->base + SDIINTEN);
+	}
+
+	return;
+}
+
 static struct mmc_host_ops ls2k_mci_ops = {
 	.request	= ls2k_mci_request,
 	.set_ios	= ls2k_mci_set_ios,
 	.get_ro		= ls2k_mci_get_ro,
 	.get_cd		= ls2k_mci_gpio_get_cd,
+	.enable_sdio_irq = ls2k_mci_enable_sdio_irq,
 };
 
 static struct ls2k_mci_pdata ls2k_mci_v1_0_pdata = {
@@ -831,6 +862,7 @@ static struct ls2k_mci_pdata ls2k_mci_v1_1_pdata = {
 };
 
 static struct ls2k_mci_pdata ls2k_mci_v1_2_pdata = {
+	 .irq_fixup = ls2k_cmd_data_fix,
 	 .version = LOONGSON_SDIO_EMMC_VER_1_2,
 };
 
@@ -887,6 +919,8 @@ static int ls2k_mci_probe(struct platform_device *pdev)
 	struct dma_chan *chan;
 	__be32 *of_property = NULL;
 	struct mmc_gpio *ctx;
+	int cd_gpio_num;
+	u64 val;
 
 	if (dev_fwnode(&pdev->dev)) {
 		if (!device_property_read_u64(&pdev->dev, "dma-mask",
@@ -916,6 +950,10 @@ static int ls2k_mci_probe(struct platform_device *pdev)
 
 	platform_device_add_data(pdev, pdata, sizeof(*pdata));
 	host->pdata = pdata;
+	val = iocsr_readq(0x20);
+	if (!strncmp((char *)&val, "2K2000AA", 8) || !strncmp((char *)&val, "2K1500AA", 8)) {
+		host->pdata->version = LOONGSON_SDIO_EMMC_VER_1_1;
+	}
 
 	spin_lock_init(&host->complete_lock);
 	tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
@@ -1004,11 +1042,10 @@ static int ls2k_mci_probe(struct platform_device *pdev)
 	}
 
 	mmc->ops	= &ls2k_mci_ops;
+	mmc->ocr_avail	= MMC_VDD_32_33|MMC_VDD_33_34;
 
 	mmc_cd_gpio_pre_setup(mmc);
 
-	mmc->ocr_avail	= MMC_VDD_32_33|MMC_VDD_33_34;
-
 	mmc->f_min	= host->clk_rate / (host->clk_div * 256);
 	mmc->f_max	= host->clk_rate / host->clk_div;
 
@@ -1031,6 +1068,16 @@ static int ls2k_mci_probe(struct platform_device *pdev)
 
 	ctx = mmc->slot.handler_priv;
 
+	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
+	    !(mmc->caps & MMC_CAP_NEEDS_POLL) && cd_gpio_inten_base) {
+		cd_gpio_num = desc_to_gpio(ctx->cd_gpio);
+		local_irq_save(flags);
+		val = readq((void *)cd_gpio_inten_base);
+		val |= (0x1 << cd_gpio_num);
+		writeq(val, (void *)cd_gpio_inten_base);
+		local_irq_restore(flags);
+		ls2k_mci_gpio_get_cd(mmc);
+	}
 	ret = mmc_add_host(mmc);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to add mmc host.\n");

drivers/mmc/host/ls2kmci.h

@@ -123,8 +123,8 @@
 #define SDIDCNT_BLKNUM_SHIFT  (12)
 
 #define SDIDSTA_RDYWAITREQ    (1<<10)
-#define SDIDSTA_SDIOIRQDETECT (1<<9)
-#define SDIDSTA_FIFOFAIL      (1<<8)
+#define SDIDSTA_FIFOFAIL      (1<<9)
+#define SDIDSTA_SDIOIRQDETECT (1<<8)
 #define SDIDSTA_CRCFAIL       (1<<7)
 #define SDIDSTA_RXCRCFAIL     (1<<6)
 #define SDIDSTA_DATATIMEOUT   (1<<5)
@@ -143,15 +143,10 @@
 #define SDIFSTA_RFEMPTY        (1<<7)
 #define SDIFSTA_COUNTMASK      (0x7f)
 
-#define SDIIMSK_RESPONSEND     (1<<14)
-#define SDIIMSK_READWAIT       (1<<13)
-#define SDIIMSK_SDIOIRQ        (1<<12)
-#define SDIIMSK_FIFOFAIL       (1<<11)
-
-
 #define SDIIMSK_RESPONSECRC    (1<<8)
 #define SDIIMSK_CMDTIMEOUT     (1<<7)
 #define SDIIMSK_CMDSENT        (1<<6)
+#define SDIIMSK_SDIOIRQ        (1<<5)
 #define SDIIMSK_PROGERR        (1<<4)
 #define SDIIMSK_TXCRCFAIL      (1<<3)
 #define SDIIMSK_RXCRCFAIL      (1<<2)

drivers/net/can/Makefile

@@ -34,6 +34,5 @@ obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
 obj-$(CONFIG_CAN_XILINXCAN)	+= xilinx_can.o
 obj-$(CONFIG_PCH_CAN)		+= pch_can.o
-obj-$(CONFIG_CAN_LSCAN)	    += ls_can/
 
 subdir-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) += -DDEBUG

sound/soc/loongson/ls-sound-es8388.c

@@ -30,7 +30,7 @@ enum {
 
 SND_SOC_DAILINK_DEFS(es8388_hifi,
 	DAILINK_COMP_ARRAY(COMP_CPU("loongson-i2s-dai")),
-	DAILINK_COMP_ARRAY(COMP_CODEC("es8328.0-0011", "es8328-hifi-analog")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("es8328.2-0011", "es8328-hifi-analog")),
 	DAILINK_COMP_ARRAY(COMP_PLATFORM("loongson-i2s")));
 
 static struct snd_soc_dai_link loongson_dai_link[] = {