优化bsp架构
This commit is contained in:
@@ -1,275 +0,0 @@
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/*********************************************************************
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* SEGGER Microcontroller GmbH *
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||||||
* The Embedded Experts *
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||||||
**********************************************************************
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* *
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||||||
* (c) 2014 - 2024 SEGGER Microcontroller GmbH *
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* *
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||||||
* www.segger.com Support: support@segger.com *
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||||||
* *
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||||||
**********************************************************************
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||||||
* *
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||||||
* All rights reserved. *
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||||||
* *
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||||||
* Redistribution and use in source and binary forms, with or *
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||||||
* without modification, are permitted provided that the following *
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||||||
* condition is met: *
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||||||
* *
|
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||||||
* - Redistributions of source code must retain the above copyright *
|
|
||||||
* notice, this condition and the following disclaimer. *
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|
||||||
* *
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|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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||||||
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
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|
||||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
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||||||
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
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|
||||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
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||||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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||||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
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||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
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|
||||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
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|
||||||
* DAMAGE. *
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* *
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||||||
**********************************************************************
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-------------------------- END-OF-HEADER -----------------------------
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File : STM32F1xx_Startup.s
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Purpose : Startup and exception handlers for STM32F1xx devices.
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Additional information:
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Preprocessor Definitions
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__NO_SYSTEM_INIT
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If defined,
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SystemInit is not called.
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If not defined,
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SystemInit is called.
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SystemInit is usually supplied by the CMSIS files.
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This file declares a weak implementation as fallback.
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__NO_SYSTEM_CLK_UPDATE
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If defined,
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SystemCoreClockUpdate is not automatically called.
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Should be defined if SystemCoreClockUpdate must not be called before main().
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If not defined,
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SystemCoreClockUpdate is called before the application entry point.
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__MEMORY_INIT
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If defined,
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MemoryInit is called after SystemInit.
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void MemoryInit(void) can be implemented to enable external
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memory controllers.
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__VECTORS_IN_RAM
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If defined,
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the vector table will be copied from Flash to RAM,
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and the vector table offset register is adjusted.
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__VTOR_CONFIG
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If defined,
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the vector table offset register is set to point to the
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application's vector table.
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__NO_FPU_ENABLE
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If defined, the FPU is explicitly not enabled,
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even if the compiler could use floating point operations.
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__SOFTFP__
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Defined by the build system.
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If not defined, the FPU is enabled for floating point operations.
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*/
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.syntax unified
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/*********************************************************************
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*
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* Global functions
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*
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**********************************************************************
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*/
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/*********************************************************************
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*
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* Reset_Handler
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*
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* Function description
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* Exception handler for reset.
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* Generic bringup of a Cortex-M system.
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*
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* Additional information
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* The stack pointer is expected to be initialized by hardware,
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* i.e. read from vectortable[0].
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* For manual initialization add
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* ldr R0, =__stack_end__
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* mov SP, R0
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*/
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.global reset_handler
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.global Reset_Handler
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.equ reset_handler, Reset_Handler
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.section .init.Reset_Handler, "ax"
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.balign 2
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.thumb_func
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Reset_Handler:
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#ifdef __SEGGER_STOP
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.extern __SEGGER_STOP_Limit_MSP
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//
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// Initialize main stack limit to 0 to disable stack checks before runtime init
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//
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movs R0, #0
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ldr R1, =__SEGGER_STOP_Limit_MSP
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str R0, [R1]
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#endif
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#ifndef __NO_SYSTEM_INIT
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//
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// Call SystemInit
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//
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bl SystemInit
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#endif
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#ifdef __MEMORY_INIT
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//
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// Call MemoryInit
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//
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bl MemoryInit
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#endif
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#ifdef __VECTORS_IN_RAM
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//
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// Copy vector table (from Flash) to RAM
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//
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ldr R0, =__vectors_start__
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ldr R1, =__vectors_end__
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ldr R2, =__vectors_ram_start__
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1:
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cmp R0, R1
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beq 2f
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ldr R3, [R0]
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str R3, [R2]
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adds R0, R0, #4
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adds R2, R2, #4
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b 1b
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2:
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#endif
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#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM)
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//
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// Configure vector table offset register
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//
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#ifdef __ARM_ARCH_6M__
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ldr R0, =0xE000ED08 // VTOR_REG
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#else
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movw R0, 0xED08 // VTOR_REG
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movt R0, 0xE000
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#endif
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#ifdef __VECTORS_IN_RAM
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ldr R1, =_vectors_ram
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#else
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ldr R1, =_vectors
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#endif
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str R1, [R0]
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#endif
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#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE)
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//
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// Enable CP11 and CP10 with CPACR |= (0xf<<20)
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//
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movw R0, 0xED88 // CPACR
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movt R0, 0xE000
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ldr R1, [R0]
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orrs R1, R1, #(0xf << 20)
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str R1, [R0]
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#endif
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//
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// Call runtime initialization, which calls main().
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//
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bl _start
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//
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// Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
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// when there is no strong definition of SystemInit.
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//
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.weak SystemInit
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//
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// Place SystemCoreClockUpdate in .init_array
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// to be called after runtime initialization
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//
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#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE)
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.section .init_array, "aw"
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.balign 4
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.word SystemCoreClockUpdate
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#endif
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/*********************************************************************
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*
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* HardFault_Handler
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*
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* Function description
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* Simple exception handler for HardFault.
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* In case of a HardFault caused by BKPT instruction without
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* debugger attached, return execution, otherwise stay in loop.
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*
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* Additional information
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||||||
* The stack pointer is expected to be initialized by hardware,
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* i.e. read from vectortable[0].
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* For manual initialization add
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* ldr R0, =__stack_end__
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* mov SP, R0
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*/
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#undef L
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#define L(label) .LHardFault_Handler_##label
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.weak HardFault_Handler
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.section .init.HardFault_Handler, "ax"
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.balign 2
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.thumb_func
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HardFault_Handler:
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//
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// Check if HardFault is caused by BKPT instruction
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//
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ldr R1, =0xE000ED2C // Load NVIC_HFSR
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ldr R2, [R1]
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cmp R2, #0 // Check NVIC_HFSR[31]
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L(hfLoop):
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bmi L(hfLoop) // Not set? Stay in HardFault Handler.
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//
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// Continue execution after BKPT instruction
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//
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#if defined(__thumb__) && !defined(__thumb2__)
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movs R0, #4
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mov R1, LR
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tst R0, R1 // Check EXC_RETURN in Link register bit 2.
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bne L(Uses_PSP)
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mrs R0, MSP // Stacking was using MSP.
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b L(Pass_StackPtr)
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L(Uses_PSP):
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mrs R0, PSP // Stacking was using PSP.
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L(Pass_StackPtr):
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#else
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tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack
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ite eq
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mrseq R0, MSP // Frame stored on MSP
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mrsne R0, PSP // Frame stored on PSP
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#endif
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//
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// Reset HardFault Status
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//
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#if defined(__thumb__) && !defined(__thumb2__)
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movs R3, #1
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lsls R3, R3, #31
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orrs R2, R3
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str R2, [R1]
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#else
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orr R2, R2, #0x80000000
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str R2, [R1]
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#endif
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//
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// Adjust return address
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//
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ldr R1, [R0, #24] // Get stored PC from stack
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adds R1, #2 // Adjust PC by 2 to skip current BKPT
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str R1, [R0, #24] // Write back adjusted PC to stack
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//
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bx LR // Return
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/*************************** End of file ****************************/
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@@ -1,293 +0,0 @@
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/*********************************************************************
|
|
||||||
* SEGGER Microcontroller GmbH *
|
|
||||||
* The Embedded Experts *
|
|
||||||
**********************************************************************
|
|
||||||
* *
|
|
||||||
* (c) 2014 - 2024 SEGGER Microcontroller GmbH *
|
|
||||||
* *
|
|
||||||
* www.segger.com Support: support@segger.com *
|
|
||||||
* *
|
|
||||||
**********************************************************************
|
|
||||||
* *
|
|
||||||
* All rights reserved. *
|
|
||||||
* *
|
|
||||||
* Redistribution and use in source and binary forms, with or *
|
|
||||||
* without modification, are permitted provided that the following *
|
|
||||||
* condition is met: *
|
|
||||||
* *
|
|
||||||
* - Redistributions of source code must retain the above copyright *
|
|
||||||
* notice, this condition and the following disclaimer. *
|
|
||||||
* *
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
|
|
||||||
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
|
|
||||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
|
|
||||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
|
|
||||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
|
|
||||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
|
|
||||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
|
|
||||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
|
|
||||||
* DAMAGE. *
|
|
||||||
* *
|
|
||||||
**********************************************************************
|
|
||||||
|
|
||||||
-------------------------- END-OF-HEADER -----------------------------
|
|
||||||
|
|
||||||
File : stm32f10x_hd_Vectors.s
|
|
||||||
Purpose : Exception and interrupt vectors for stm32f10x_hd devices.
|
|
||||||
|
|
||||||
Additional information:
|
|
||||||
Preprocessor Definitions
|
|
||||||
__NO_EXTERNAL_INTERRUPTS
|
|
||||||
If defined,
|
|
||||||
the vector table will contain only the internal exceptions
|
|
||||||
and interrupts.
|
|
||||||
__VECTORS_IN_RAM
|
|
||||||
If defined,
|
|
||||||
an area of RAM, large enough to store the vector table,
|
|
||||||
will be reserved.
|
|
||||||
|
|
||||||
__OPTIMIZATION_SMALL
|
|
||||||
If defined,
|
|
||||||
all weak definitions of interrupt handlers will share the
|
|
||||||
same implementation.
|
|
||||||
If not defined,
|
|
||||||
all weak definitions of interrupt handlers will be defined
|
|
||||||
with their own implementation.
|
|
||||||
*/
|
|
||||||
.syntax unified
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
*
|
|
||||||
* Macros
|
|
||||||
*
|
|
||||||
**********************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
//
|
|
||||||
// Directly place a vector (word) in the vector table
|
|
||||||
//
|
|
||||||
.macro VECTOR Name=
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.code 16
|
|
||||||
.word \Name
|
|
||||||
.endm
|
|
||||||
|
|
||||||
//
|
|
||||||
// Declare an exception handler with a weak definition
|
|
||||||
//
|
|
||||||
.macro EXC_HANDLER Name=
|
|
||||||
//
|
|
||||||
// Insert vector in vector table
|
|
||||||
//
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.word \Name
|
|
||||||
//
|
|
||||||
// Insert dummy handler in init section
|
|
||||||
//
|
|
||||||
.section .init.\Name, "ax"
|
|
||||||
.thumb_func
|
|
||||||
.weak \Name
|
|
||||||
.balign 2
|
|
||||||
\Name:
|
|
||||||
1: b 1b // Endless loop
|
|
||||||
.endm
|
|
||||||
|
|
||||||
//
|
|
||||||
// Declare an interrupt handler with a weak definition
|
|
||||||
//
|
|
||||||
.macro ISR_HANDLER Name=
|
|
||||||
//
|
|
||||||
// Insert vector in vector table
|
|
||||||
//
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.word \Name
|
|
||||||
//
|
|
||||||
// Insert dummy handler in init section
|
|
||||||
//
|
|
||||||
#if defined(__OPTIMIZATION_SMALL)
|
|
||||||
.section .init, "ax"
|
|
||||||
.weak \Name
|
|
||||||
.thumb_set \Name,Dummy_Handler
|
|
||||||
#else
|
|
||||||
.section .init.\Name, "ax"
|
|
||||||
.thumb_func
|
|
||||||
.weak \Name
|
|
||||||
.balign 2
|
|
||||||
\Name:
|
|
||||||
1: b 1b // Endless loop
|
|
||||||
#endif
|
|
||||||
.endm
|
|
||||||
|
|
||||||
//
|
|
||||||
// Place a reserved vector in vector table
|
|
||||||
//
|
|
||||||
.macro ISR_RESERVED
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.word 0
|
|
||||||
.endm
|
|
||||||
|
|
||||||
//
|
|
||||||
// Place a reserved vector in vector table
|
|
||||||
//
|
|
||||||
.macro ISR_RESERVED_DUMMY
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.word Dummy_Handler
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
*
|
|
||||||
* Externals
|
|
||||||
*
|
|
||||||
**********************************************************************
|
|
||||||
*/
|
|
||||||
.extern __stack_end__
|
|
||||||
.extern Reset_Handler
|
|
||||||
.extern HardFault_Handler
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
*
|
|
||||||
* Global functions
|
|
||||||
*
|
|
||||||
**********************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
*
|
|
||||||
* Setup of the vector table and weak definition of interrupt handlers
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
.section .vectors, "ax"
|
|
||||||
.code 16
|
|
||||||
.balign 256
|
|
||||||
.global _vectors
|
|
||||||
_vectors:
|
|
||||||
//
|
|
||||||
// Internal exceptions and interrupts
|
|
||||||
//
|
|
||||||
VECTOR __stack_end__
|
|
||||||
VECTOR Reset_Handler
|
|
||||||
EXC_HANDLER NMI_Handler
|
|
||||||
VECTOR HardFault_Handler
|
|
||||||
#ifdef __ARM_ARCH_6M__
|
|
||||||
ISR_RESERVED
|
|
||||||
ISR_RESERVED
|
|
||||||
ISR_RESERVED
|
|
||||||
#else
|
|
||||||
EXC_HANDLER MemManage_Handler
|
|
||||||
EXC_HANDLER BusFault_Handler
|
|
||||||
EXC_HANDLER UsageFault_Handler
|
|
||||||
#endif
|
|
||||||
ISR_RESERVED
|
|
||||||
ISR_RESERVED
|
|
||||||
ISR_RESERVED
|
|
||||||
ISR_RESERVED
|
|
||||||
EXC_HANDLER SVC_Handler
|
|
||||||
#ifdef __ARM_ARCH_6M__
|
|
||||||
ISR_RESERVED
|
|
||||||
#else
|
|
||||||
EXC_HANDLER DebugMon_Handler
|
|
||||||
#endif
|
|
||||||
ISR_RESERVED
|
|
||||||
EXC_HANDLER PendSV_Handler
|
|
||||||
EXC_HANDLER SysTick_Handler
|
|
||||||
//
|
|
||||||
// External interrupts
|
|
||||||
//
|
|
||||||
#ifndef __NO_EXTERNAL_INTERRUPTS
|
|
||||||
ISR_HANDLER WWDG_IRQHandler
|
|
||||||
ISR_HANDLER PVD_IRQHandler
|
|
||||||
ISR_HANDLER TAMPER_IRQHandler
|
|
||||||
ISR_HANDLER RTC_IRQHandler
|
|
||||||
ISR_HANDLER FLASH_IRQHandler
|
|
||||||
ISR_HANDLER RCC_IRQHandler
|
|
||||||
ISR_HANDLER EXTI0_IRQHandler
|
|
||||||
ISR_HANDLER EXTI1_IRQHandler
|
|
||||||
ISR_HANDLER EXTI2_IRQHandler
|
|
||||||
ISR_HANDLER EXTI3_IRQHandler
|
|
||||||
ISR_HANDLER EXTI4_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel1_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel2_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel3_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel4_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel5_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel6_IRQHandler
|
|
||||||
ISR_HANDLER DMA1_Channel7_IRQHandler
|
|
||||||
ISR_HANDLER ADC1_2_IRQHandler
|
|
||||||
ISR_HANDLER USB_HP_CAN1_TX_IRQHandler
|
|
||||||
ISR_HANDLER USB_LP_CAN1_RX0_IRQHandler
|
|
||||||
ISR_HANDLER CAN1_RX1_IRQHandler
|
|
||||||
ISR_HANDLER CAN1_SCE_IRQHandler
|
|
||||||
ISR_HANDLER EXTI9_5_IRQHandler
|
|
||||||
ISR_HANDLER TIM1_BRK_IRQHandler
|
|
||||||
ISR_HANDLER TIM1_UP_IRQHandler
|
|
||||||
ISR_HANDLER TIM1_TRG_COM_IRQHandler
|
|
||||||
ISR_HANDLER TIM1_CC_IRQHandler
|
|
||||||
ISR_HANDLER TIM2_IRQHandler
|
|
||||||
ISR_HANDLER TIM3_IRQHandler
|
|
||||||
ISR_HANDLER TIM4_IRQHandler
|
|
||||||
ISR_HANDLER I2C1_EV_IRQHandler
|
|
||||||
ISR_HANDLER I2C1_ER_IRQHandler
|
|
||||||
ISR_HANDLER I2C2_EV_IRQHandler
|
|
||||||
ISR_HANDLER I2C2_ER_IRQHandler
|
|
||||||
ISR_HANDLER SPI1_IRQHandler
|
|
||||||
ISR_HANDLER SPI2_IRQHandler
|
|
||||||
ISR_HANDLER USART1_IRQHandler
|
|
||||||
ISR_HANDLER USART2_IRQHandler
|
|
||||||
ISR_HANDLER USART3_IRQHandler
|
|
||||||
ISR_HANDLER EXTI15_10_IRQHandler
|
|
||||||
ISR_HANDLER RTCAlarm_IRQHandler
|
|
||||||
ISR_HANDLER USBWakeUp_IRQHandler
|
|
||||||
ISR_HANDLER TIM8_BRK_IRQHandler
|
|
||||||
ISR_HANDLER TIM8_UP_IRQHandler
|
|
||||||
ISR_HANDLER TIM8_TRG_COM_IRQHandler
|
|
||||||
ISR_HANDLER TIM8_CC_IRQHandler
|
|
||||||
ISR_HANDLER ADC3_IRQHandler
|
|
||||||
ISR_HANDLER FSMC_IRQHandler
|
|
||||||
ISR_HANDLER SDIO_IRQHandler
|
|
||||||
ISR_HANDLER TIM5_IRQHandler
|
|
||||||
ISR_HANDLER SPI3_IRQHandler
|
|
||||||
ISR_HANDLER UART4_IRQHandler
|
|
||||||
ISR_HANDLER UART5_IRQHandler
|
|
||||||
ISR_HANDLER TIM6_IRQHandler
|
|
||||||
ISR_HANDLER TIM7_IRQHandler
|
|
||||||
ISR_HANDLER DMA2_Channel1_IRQHandler
|
|
||||||
ISR_HANDLER DMA2_Channel2_IRQHandler
|
|
||||||
ISR_HANDLER DMA2_Channel3_IRQHandler
|
|
||||||
ISR_HANDLER DMA2_Channel4_5_IRQHandler
|
|
||||||
#endif
|
|
||||||
//
|
|
||||||
.section .vectors, "ax"
|
|
||||||
_vectors_end:
|
|
||||||
|
|
||||||
#ifdef __VECTORS_IN_RAM
|
|
||||||
//
|
|
||||||
// Reserve space with the size of the vector table
|
|
||||||
// in the designated RAM section.
|
|
||||||
//
|
|
||||||
.section .vectors_ram, "ax"
|
|
||||||
.balign 256
|
|
||||||
.global _vectors_ram
|
|
||||||
|
|
||||||
_vectors_ram:
|
|
||||||
.space _vectors_end - _vectors, 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
*
|
|
||||||
* Dummy handler to be used for reserved interrupt vectors
|
|
||||||
* and weak implementation of interrupts.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
.section .init.Dummy_Handler, "ax"
|
|
||||||
.thumb_func
|
|
||||||
.weak Dummy_Handler
|
|
||||||
.balign 2
|
|
||||||
Dummy_Handler:
|
|
||||||
1: b 1b // Endless loop
|
|
||||||
|
|
||||||
|
|
||||||
/*************************** End of file ****************************/
|
|
||||||
Reference in New Issue
Block a user