diff --git a/System/Startup/iar/startup_stm32f10x_cl.s b/System/Startup/Iar/startup_stm32f10x_cl.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_cl.s rename to System/Startup/Iar/startup_stm32f10x_cl.s diff --git a/System/Startup/iar/startup_stm32f10x_hd.s b/System/Startup/Iar/startup_stm32f10x_hd.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_hd.s rename to System/Startup/Iar/startup_stm32f10x_hd.s diff --git a/System/Startup/iar/startup_stm32f10x_hd_vl.s b/System/Startup/Iar/startup_stm32f10x_hd_vl.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_hd_vl.s rename to System/Startup/Iar/startup_stm32f10x_hd_vl.s diff --git a/System/Startup/iar/startup_stm32f10x_ld.s b/System/Startup/Iar/startup_stm32f10x_ld.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_ld.s rename to System/Startup/Iar/startup_stm32f10x_ld.s diff --git a/System/Startup/iar/startup_stm32f10x_ld_vl.s b/System/Startup/Iar/startup_stm32f10x_ld_vl.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_ld_vl.s rename to System/Startup/Iar/startup_stm32f10x_ld_vl.s diff --git a/System/Startup/iar/startup_stm32f10x_md.s b/System/Startup/Iar/startup_stm32f10x_md.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_md.s rename to System/Startup/Iar/startup_stm32f10x_md.s diff --git a/System/Startup/iar/startup_stm32f10x_md_vl.s b/System/Startup/Iar/startup_stm32f10x_md_vl.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_md_vl.s rename to System/Startup/Iar/startup_stm32f10x_md_vl.s diff --git a/System/Startup/iar/startup_stm32f10x_xl.s b/System/Startup/Iar/startup_stm32f10x_xl.s similarity index 100% rename from System/Startup/iar/startup_stm32f10x_xl.s rename to System/Startup/Iar/startup_stm32f10x_xl.s diff --git a/System/Startup/arm/startup_stm32f10x_cl.s b/System/Startup/Keil/startup_stm32f10x_cl.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_cl.s rename to System/Startup/Keil/startup_stm32f10x_cl.s diff --git a/System/Startup/arm/startup_stm32f10x_hd.s b/System/Startup/Keil/startup_stm32f10x_hd.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_hd.s rename to System/Startup/Keil/startup_stm32f10x_hd.s diff --git a/System/Startup/arm/startup_stm32f10x_hd_vl.s b/System/Startup/Keil/startup_stm32f10x_hd_vl.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_hd_vl.s rename to System/Startup/Keil/startup_stm32f10x_hd_vl.s diff --git a/System/Startup/arm/startup_stm32f10x_ld.s b/System/Startup/Keil/startup_stm32f10x_ld.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_ld.s rename to System/Startup/Keil/startup_stm32f10x_ld.s diff --git a/System/Startup/arm/startup_stm32f10x_ld_vl.s b/System/Startup/Keil/startup_stm32f10x_ld_vl.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_ld_vl.s rename to System/Startup/Keil/startup_stm32f10x_ld_vl.s diff --git a/System/Startup/arm/startup_stm32f10x_md.s b/System/Startup/Keil/startup_stm32f10x_md.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_md.s rename to System/Startup/Keil/startup_stm32f10x_md.s diff --git a/System/Startup/arm/startup_stm32f10x_md_vl.s b/System/Startup/Keil/startup_stm32f10x_md_vl.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_md_vl.s rename to System/Startup/Keil/startup_stm32f10x_md_vl.s diff --git a/System/Startup/arm/startup_stm32f10x_xl.s b/System/Startup/Keil/startup_stm32f10x_xl.s similarity index 100% rename from System/Startup/arm/startup_stm32f10x_xl.s rename to System/Startup/Keil/startup_stm32f10x_xl.s diff --git a/System/Startup/Ses/STM32F1xx_Startup.s b/System/Startup/Ses/STM32F1xx_Startup.s deleted file mode 100644 index 6221dfb..0000000 --- a/System/Startup/Ses/STM32F1xx_Startup.s +++ /dev/null @@ -1,275 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2024 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : STM32F1xx_Startup.s -Purpose : Startup and exception handlers for STM32F1xx devices. - -Additional information: - Preprocessor Definitions - __NO_SYSTEM_INIT - If defined, - SystemInit is not called. - If not defined, - SystemInit is called. - SystemInit is usually supplied by the CMSIS files. - This file declares a weak implementation as fallback. - - __NO_SYSTEM_CLK_UPDATE - If defined, - SystemCoreClockUpdate is not automatically called. - Should be defined if SystemCoreClockUpdate must not be called before main(). - If not defined, - SystemCoreClockUpdate is called before the application entry point. - - __MEMORY_INIT - If defined, - MemoryInit is called after SystemInit. - void MemoryInit(void) can be implemented to enable external - memory controllers. - - __VECTORS_IN_RAM - If defined, - the vector table will be copied from Flash to RAM, - and the vector table offset register is adjusted. - - __VTOR_CONFIG - If defined, - the vector table offset register is set to point to the - application's vector table. - - __NO_FPU_ENABLE - If defined, the FPU is explicitly not enabled, - even if the compiler could use floating point operations. - - __SOFTFP__ - Defined by the build system. - If not defined, the FPU is enabled for floating point operations. -*/ - - .syntax unified - - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* Reset_Handler -* -* Function description -* Exception handler for reset. -* Generic bringup of a Cortex-M system. -* -* Additional information -* The stack pointer is expected to be initialized by hardware, -* i.e. read from vectortable[0]. -* For manual initialization add -* ldr R0, =__stack_end__ -* mov SP, R0 -*/ - .global reset_handler - .global Reset_Handler - .equ reset_handler, Reset_Handler - .section .init.Reset_Handler, "ax" - .balign 2 - .thumb_func -Reset_Handler: -#ifdef __SEGGER_STOP - .extern __SEGGER_STOP_Limit_MSP - // - // Initialize main stack limit to 0 to disable stack checks before runtime init - // - movs R0, #0 - ldr R1, =__SEGGER_STOP_Limit_MSP - str R0, [R1] -#endif -#ifndef __NO_SYSTEM_INIT - // - // Call SystemInit - // - bl SystemInit -#endif -#ifdef __MEMORY_INIT - // - // Call MemoryInit - // - bl MemoryInit -#endif -#ifdef __VECTORS_IN_RAM - // - // Copy vector table (from Flash) to RAM - // - ldr R0, =__vectors_start__ - ldr R1, =__vectors_end__ - ldr R2, =__vectors_ram_start__ -1: - cmp R0, R1 - beq 2f - ldr R3, [R0] - str R3, [R2] - adds R0, R0, #4 - adds R2, R2, #4 - b 1b -2: -#endif - -#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM) - // - // Configure vector table offset register - // -#ifdef __ARM_ARCH_6M__ - ldr R0, =0xE000ED08 // VTOR_REG -#else - movw R0, 0xED08 // VTOR_REG - movt R0, 0xE000 -#endif -#ifdef __VECTORS_IN_RAM - ldr R1, =_vectors_ram -#else - ldr R1, =_vectors -#endif - str R1, [R0] -#endif -#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE) - // - // Enable CP11 and CP10 with CPACR |= (0xf<<20) - // - movw R0, 0xED88 // CPACR - movt R0, 0xE000 - ldr R1, [R0] - orrs R1, R1, #(0xf << 20) - str R1, [R0] -#endif - // - // Call runtime initialization, which calls main(). - // - bl _start - - // - // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, - // when there is no strong definition of SystemInit. - // - .weak SystemInit - // - // Place SystemCoreClockUpdate in .init_array - // to be called after runtime initialization - // -#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE) - .section .init_array, "aw" - .balign 4 - .word SystemCoreClockUpdate -#endif - -/********************************************************************* -* -* HardFault_Handler -* -* Function description -* Simple exception handler for HardFault. -* In case of a HardFault caused by BKPT instruction without -* debugger attached, return execution, otherwise stay in loop. -* -* Additional information -* The stack pointer is expected to be initialized by hardware, -* i.e. read from vectortable[0]. -* For manual initialization add -* ldr R0, =__stack_end__ -* mov SP, R0 -*/ - -#undef L -#define L(label) .LHardFault_Handler_##label - - .weak HardFault_Handler - .section .init.HardFault_Handler, "ax" - .balign 2 - .thumb_func -HardFault_Handler: - // - // Check if HardFault is caused by BKPT instruction - // - ldr R1, =0xE000ED2C // Load NVIC_HFSR - ldr R2, [R1] - cmp R2, #0 // Check NVIC_HFSR[31] - -L(hfLoop): - bmi L(hfLoop) // Not set? Stay in HardFault Handler. - // - // Continue execution after BKPT instruction - // -#if defined(__thumb__) && !defined(__thumb2__) - movs R0, #4 - mov R1, LR - tst R0, R1 // Check EXC_RETURN in Link register bit 2. - bne L(Uses_PSP) - mrs R0, MSP // Stacking was using MSP. - b L(Pass_StackPtr) -L(Uses_PSP): - mrs R0, PSP // Stacking was using PSP. -L(Pass_StackPtr): -#else - tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack - ite eq - mrseq R0, MSP // Frame stored on MSP - mrsne R0, PSP // Frame stored on PSP -#endif - // - // Reset HardFault Status - // -#if defined(__thumb__) && !defined(__thumb2__) - movs R3, #1 - lsls R3, R3, #31 - orrs R2, R3 - str R2, [R1] -#else - orr R2, R2, #0x80000000 - str R2, [R1] -#endif - // - // Adjust return address - // - ldr R1, [R0, #24] // Get stored PC from stack - adds R1, #2 // Adjust PC by 2 to skip current BKPT - str R1, [R0, #24] // Write back adjusted PC to stack - // - bx LR // Return - -/*************************** End of file ****************************/ diff --git a/System/Startup/Ses/stm32f10x_hd_Vectors.s b/System/Startup/Ses/stm32f10x_hd_Vectors.s deleted file mode 100644 index 50a6341..0000000 --- a/System/Startup/Ses/stm32f10x_hd_Vectors.s +++ /dev/null @@ -1,293 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2024 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : stm32f10x_hd_Vectors.s -Purpose : Exception and interrupt vectors for stm32f10x_hd devices. - -Additional information: - Preprocessor Definitions - __NO_EXTERNAL_INTERRUPTS - If defined, - the vector table will contain only the internal exceptions - and interrupts. - __VECTORS_IN_RAM - If defined, - an area of RAM, large enough to store the vector table, - will be reserved. - - __OPTIMIZATION_SMALL - If defined, - all weak definitions of interrupt handlers will share the - same implementation. - If not defined, - all weak definitions of interrupt handlers will be defined - with their own implementation. -*/ - .syntax unified - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ - -// -// Directly place a vector (word) in the vector table -// -.macro VECTOR Name= - .section .vectors, "ax" - .code 16 - .word \Name -.endm - -// -// Declare an exception handler with a weak definition -// -.macro EXC_HANDLER Name= - // - // Insert vector in vector table - // - .section .vectors, "ax" - .word \Name - // - // Insert dummy handler in init section - // - .section .init.\Name, "ax" - .thumb_func - .weak \Name - .balign 2 -\Name: - 1: b 1b // Endless loop -.endm - -// -// Declare an interrupt handler with a weak definition -// -.macro ISR_HANDLER Name= - // - // Insert vector in vector table - // - .section .vectors, "ax" - .word \Name - // - // Insert dummy handler in init section - // -#if defined(__OPTIMIZATION_SMALL) - .section .init, "ax" - .weak \Name - .thumb_set \Name,Dummy_Handler -#else - .section .init.\Name, "ax" - .thumb_func - .weak \Name - .balign 2 -\Name: - 1: b 1b // Endless loop -#endif -.endm - -// -// Place a reserved vector in vector table -// -.macro ISR_RESERVED - .section .vectors, "ax" - .word 0 -.endm - -// -// Place a reserved vector in vector table -// -.macro ISR_RESERVED_DUMMY - .section .vectors, "ax" - .word Dummy_Handler -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern __stack_end__ - .extern Reset_Handler - .extern HardFault_Handler - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ - -/********************************************************************* -* -* Setup of the vector table and weak definition of interrupt handlers -* -*/ - .section .vectors, "ax" - .code 16 - .balign 256 - .global _vectors -_vectors: - // - // Internal exceptions and interrupts - // - VECTOR __stack_end__ - VECTOR Reset_Handler - EXC_HANDLER NMI_Handler - VECTOR HardFault_Handler -#ifdef __ARM_ARCH_6M__ - ISR_RESERVED - ISR_RESERVED - ISR_RESERVED -#else - EXC_HANDLER MemManage_Handler - EXC_HANDLER BusFault_Handler - EXC_HANDLER UsageFault_Handler -#endif - ISR_RESERVED - ISR_RESERVED - ISR_RESERVED - ISR_RESERVED - EXC_HANDLER SVC_Handler -#ifdef __ARM_ARCH_6M__ - ISR_RESERVED -#else - EXC_HANDLER DebugMon_Handler -#endif - ISR_RESERVED - EXC_HANDLER PendSV_Handler - EXC_HANDLER SysTick_Handler - // - // External interrupts - // -#ifndef __NO_EXTERNAL_INTERRUPTS - ISR_HANDLER WWDG_IRQHandler - ISR_HANDLER PVD_IRQHandler - ISR_HANDLER TAMPER_IRQHandler - ISR_HANDLER RTC_IRQHandler - ISR_HANDLER FLASH_IRQHandler - ISR_HANDLER RCC_IRQHandler - ISR_HANDLER EXTI0_IRQHandler - ISR_HANDLER EXTI1_IRQHandler - ISR_HANDLER EXTI2_IRQHandler - ISR_HANDLER EXTI3_IRQHandler - ISR_HANDLER EXTI4_IRQHandler - ISR_HANDLER DMA1_Channel1_IRQHandler - ISR_HANDLER DMA1_Channel2_IRQHandler - ISR_HANDLER DMA1_Channel3_IRQHandler - ISR_HANDLER DMA1_Channel4_IRQHandler - ISR_HANDLER DMA1_Channel5_IRQHandler - ISR_HANDLER DMA1_Channel6_IRQHandler - ISR_HANDLER DMA1_Channel7_IRQHandler - ISR_HANDLER ADC1_2_IRQHandler - ISR_HANDLER USB_HP_CAN1_TX_IRQHandler - ISR_HANDLER USB_LP_CAN1_RX0_IRQHandler - ISR_HANDLER CAN1_RX1_IRQHandler - ISR_HANDLER CAN1_SCE_IRQHandler - ISR_HANDLER EXTI9_5_IRQHandler - ISR_HANDLER TIM1_BRK_IRQHandler - ISR_HANDLER TIM1_UP_IRQHandler - ISR_HANDLER TIM1_TRG_COM_IRQHandler - ISR_HANDLER TIM1_CC_IRQHandler - ISR_HANDLER TIM2_IRQHandler - ISR_HANDLER TIM3_IRQHandler - ISR_HANDLER TIM4_IRQHandler - ISR_HANDLER I2C1_EV_IRQHandler - ISR_HANDLER I2C1_ER_IRQHandler - ISR_HANDLER I2C2_EV_IRQHandler - ISR_HANDLER I2C2_ER_IRQHandler - ISR_HANDLER SPI1_IRQHandler - ISR_HANDLER SPI2_IRQHandler - ISR_HANDLER USART1_IRQHandler - ISR_HANDLER USART2_IRQHandler - ISR_HANDLER USART3_IRQHandler - ISR_HANDLER EXTI15_10_IRQHandler - ISR_HANDLER RTCAlarm_IRQHandler - ISR_HANDLER USBWakeUp_IRQHandler - ISR_HANDLER TIM8_BRK_IRQHandler - ISR_HANDLER TIM8_UP_IRQHandler - ISR_HANDLER TIM8_TRG_COM_IRQHandler - ISR_HANDLER TIM8_CC_IRQHandler - ISR_HANDLER ADC3_IRQHandler - ISR_HANDLER FSMC_IRQHandler - ISR_HANDLER SDIO_IRQHandler - ISR_HANDLER TIM5_IRQHandler - ISR_HANDLER SPI3_IRQHandler - ISR_HANDLER UART4_IRQHandler - ISR_HANDLER UART5_IRQHandler - ISR_HANDLER TIM6_IRQHandler - ISR_HANDLER TIM7_IRQHandler - ISR_HANDLER DMA2_Channel1_IRQHandler - ISR_HANDLER DMA2_Channel2_IRQHandler - ISR_HANDLER DMA2_Channel3_IRQHandler - ISR_HANDLER DMA2_Channel4_5_IRQHandler -#endif - // - .section .vectors, "ax" -_vectors_end: - -#ifdef __VECTORS_IN_RAM - // - // Reserve space with the size of the vector table - // in the designated RAM section. - // - .section .vectors_ram, "ax" - .balign 256 - .global _vectors_ram - -_vectors_ram: - .space _vectors_end - _vectors, 0 -#endif - -/********************************************************************* -* -* Dummy handler to be used for reserved interrupt vectors -* and weak implementation of interrupts. -* -*/ - .section .init.Dummy_Handler, "ax" - .thumb_func - .weak Dummy_Handler - .balign 2 -Dummy_Handler: - 1: b 1b // Endless loop - - -/*************************** End of file ****************************/