openloongarch-uboot-2022.04/arch/loongarch/dts/ls2p500_evb.dts

#include "ls2p500.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "loongson-2p500";

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon";
	};

	sysinfo-smbios {
		compatible = "u-boot,sysinfo-smbios";
		u-boot,dm-pre-reloc;

		smbios {
			system {
				manufacturer = "Loongson";
				product = "LS2P500";
			};

			baseboard {
				manufacturer = "Loongson";
				product = "LS2P500-EVB";
			};

			chassis {
				manufacturer = "Loongson";
				product = "LS2P500-EVB";
			};
		};
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg =  <0x90000000 0x00000000 0 0x10000000
			0x90000000 0x90000000 0 0x30000000>;
		u-boot,dm-pre-reloc;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bootparam: bootparam_region {
			reg = <0x90000000 0x0f000000 0x0 0x1000000>;
			no-map;
		};
	};

	mc0: ram@0 {
		compatible = "loongson,ls2p500-ddr";
		u-boot,dm-pre-reloc;

		soc-config-reg = <0x14000100>;
		mc-disable-offs = <0>;
		mc-default-offs = <1>;

		sdram-type = "ddr3";	// ddr2/ddr3
		dimm-type = "udimm";	// rdimm/udimm/sodimm

		cs-map = <0x1>;		// bit map: 	bit0 -- cs0
					// 		bit1 -- cs1
					//		bit2 -- cs2
					//		bit3 -- cs3

		data-width = <32>;	// 16/32/64
		sdram-width = <16>;	// 8/16
		sdram-banks = <8>;	// 2/4/8
		sdram-rows = <15>;
		sdram-cols = <10>;

		clk-latency = <0x30>;
		rd-latency = <0x9>;
		wr-latency = <0x4>;
		cmd-timing-mode = <1>;	// 0: 1T mode; 1(default): 2T mode; 2: 3T mode.

		// To enable the feature below, uncomment it.
		// ecc-enable;
		/* addr-mirror; */
		/* multi-channel; */
		/* reset-revert; */
	};

};

&spi0 {
	status = "okay";

	spi-flash@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <25000000>; /* input clock */
		reg = <0>; /* CS0 */
	};
};

&i2c0 {
    status = "okay";

    // eeprom@57 {
    //     compatible = "atmel,24c32";
    //     reg = <0x57>;
    //     pagesize = <32>;
    // };
};


&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&eth_phy0>;

	mdio0: mdio@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		eth_phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&eth_phy1>;

	mdio1: mdio@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		eth_phy1: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&emmc0 {
	status = "okay";
};