From 8305551cb568192abcf94ef51b4c5cf6906dff12 Mon Sep 17 00:00:00 2001 From: maoxiaochuan Date: Fri, 27 Dec 2024 23:50:09 +0800 Subject: [PATCH] loongarch: mach: add mach nedd header file Signed-off-by: maoxiaochuan --- arch/loongarch/Makefile | 1 + arch/loongarch/include/asm/mach/boot_param.h | 139 ++++ arch/loongarch/include/asm/mach/irq.h | 88 +++ arch/loongarch/include/asm/mach/loongson-2k.h | 742 ++++++++++++++++++ .../include/asm/mach/loongson-2k300.h | 123 +++ arch/loongarch/include/asm/mach/loongson.h | 163 ++++ arch/loongarch/include/asm/mach/topology.h | 26 + 7 files changed, 1282 insertions(+) create mode 100644 arch/loongarch/include/asm/mach/boot_param.h create mode 100644 arch/loongarch/include/asm/mach/irq.h create mode 100644 arch/loongarch/include/asm/mach/loongson-2k.h create mode 100644 arch/loongarch/include/asm/mach/loongson-2k300.h create mode 100644 arch/loongarch/include/asm/mach/loongson.h create mode 100644 arch/loongarch/include/asm/mach/topology.h diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile index 2b13d918c..2fda81e8c 100644 --- a/arch/loongarch/Makefile +++ b/arch/loongarch/Makefile @@ -63,6 +63,7 @@ cflags-y += -mabi=lp64s -mcmodel=normal endif cflags-y += -pipe $(CC_FLAGS_NO_FPU) +cflags-y += -I$(srctree)/arch/loongarch/include/asm/mach LDFLAGS_vmlinux += -static -n -nostdlib # When the assembler supports explicit relocation hint, we must use it. diff --git a/arch/loongarch/include/asm/mach/boot_param.h b/arch/loongarch/include/asm/mach/boot_param.h new file mode 100644 index 000000000..169dee366 --- /dev/null +++ b/arch/loongarch/include/asm/mach/boot_param.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ +#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ + +#ifdef CONFIG_VT +#include +#endif + +#define ADDRESS_TYPE_SYSRAM 1 +#define ADDRESS_TYPE_RESERVED 2 +#define ADDRESS_TYPE_ACPI 3 +#define ADDRESS_TYPE_NVS 4 +#define ADDRESS_TYPE_PMEM 5 + +#define EFI_RUNTIME_MAP_START 100 +#define LOONGSON3_BOOT_MEM_MAP_MAX 128 + +#define LOONGSON_EFIBOOT_SIGNATURE "BPI" +#define LOONGSON_MEM_SIGNATURE "MEM" +#define LOONGSON_VBIOS_SIGNATURE "VBIOS" +#define LOONGSON_SCREENINFO_SIGNATURE "SINFO" + +/* Values for Version BPI */ +enum bpi_version { + BPI_VERSION_V1 = 1000, /* Signature="BPI01000" */ + BPI_VERSION_V2 = 1001, /* Signature="BPI01001" */ + BPI_VERSION_V3 = 1002, /* Signature="BPI01002" */ +}; + +/* Flags in bootparamsinterface */ +#define BPI_FLAGS_UEFI_SUPPORTED BIT(0) +#define BPI_FLAGS_SOC_CPU BIT(1) + +struct _extention_list_hdr { + u64 signature; + u32 length; + u8 revision; + u8 checksum; + u64 next_offset; +} __packed; + +struct boot_params { + u64 signature; /* {"B", "P", "I", "0", "1", ... } */ + void *systemtable; + u64 extlist_offset; + u64 flags; +} __packed; + +struct loongsonlist_mem_map_legacy { + struct _extention_list_hdr header; /* {"M", "E", "M"} */ + u8 map_count; + struct loongson_mem_map { + u32 mem_type; + u64 mem_start; + u64 mem_size; + } __packed map[LOONGSON3_BOOT_MEM_MAP_MAX]; +} __packed; + +struct loongsonlist_mem_map { + struct _extention_list_hdr header; /* {"M", "E", "M"} */ + u8 map_count; + u32 desc_version; + struct efi_mmap { + u32 mem_type; + u32 padding; + u64 mem_start; + u64 mem_vaddr; + u64 mem_size; + u64 attribute; + } __packed map[LOONGSON3_BOOT_MEM_MAP_MAX]; +} __packed; + +struct loongsonlist_vbios { + struct _extention_list_hdr header; /* {"V", "B", "I", "O", "S"} */ + u64 vbios_addr; +} __packed; + +struct loongsonlist_screeninfo{ + struct _extention_list_hdr header; /* {"S", "I", "N", "F", "O"} */ + struct screen_info si; +} __packed; + +// struct loongson_board_info { +// int bios_size; +// char *bios_vendor; +// char *bios_version; +// char *bios_release_date; +// char *board_name; +// char *board_vendor; +// }; + +// struct loongson_system_configuration { +// int bpi_ver; +// int nr_cpus; +// int nr_nodes; +// int nr_io_pics; +// int boot_cpu_id; +// int cores_per_node; +// int cores_per_package; +// char *cpuname; +// u64 suspend_addr; +// u64 vgabios_addr; +// int is_soc_cpu; +// }; + +extern void *loongson_fdt_blob; +extern u32 __dtb_loongson3_ls7a_begin[]; +extern u32 __dtb_ls2k500_hl_mb_begin[]; +extern u32 __dtb_ls2k500_mini_dp_begin[]; +extern u32 __dtb_ls2k500_dayu400_mb_begin[]; +extern u32 __dtb_ls2k500_modi_hct_begin[]; +extern u32 __dtb_ls2k500_zhengtai_pcs1800_v10_begin[]; +extern u32 __dtb_ls2k500_jiaoqian_v10_begin[]; +extern u32 __dtb_ls2k500_zjjz_begin[]; +extern u32 __dtb_ls2k1000_jl_mb_begin[]; +extern u32 __dtb_ls2k1000_jl_mb_mu_begin[]; +extern u32 __dtb_ls2k1000_jl_mb_nodvo_begin[]; +extern u32 __dtb_ls2k1000_dp_begin[]; +extern u32 __dtb_ls2k1000_dp_i2s_begin[]; +extern u32 __dtb_ls2k1000_dp_test_begin[]; +extern u32 __dtb_ls2k1000_dp_factory_begin[]; +extern u32 __dtb_ksec_hac_mb_begin[]; +extern u32 __dtb_gbkpdm0_v10_begin[]; +extern u32 __dtb_gbkpdm0_litong_begin[]; +extern u32 __dtb_ls2k1000_cl_mb_begin[]; +extern u32 __dtb_ls2k1000_c4g_mb001_begin[]; +extern u32 __dtb_ls2k1000_znwlidzd_litong_begin[]; +extern u32 __dtb_ls2p500_evb_begin[]; +extern u32 __dtb_ls2p500_rsj_mb_v10_begin[]; +extern u32 __dtb_ls2p500_gbkpjm0_v10_begin[]; +extern u32 __dtb_ls2k300_mini_dp_begin[]; +extern u32 __dtb_ls2k300_vanguard_pi_begin[]; +extern u32 __dtb_ls2k300_tewei_begin[]; +extern char __dtb_start[]; +extern struct boot_params *efi_bp; +extern struct loongson_board_info b_info; +extern struct loongsonlist_mem_map *loongson_mem_map; +extern struct loongson_system_configuration loongson_sysconf; +#endif diff --git a/arch/loongarch/include/asm/mach/irq.h b/arch/loongarch/include/asm/mach/irq.h new file mode 100644 index 000000000..b4dc6c667 --- /dev/null +++ b/arch/loongarch/include/asm/mach/irq.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_LOONGSON64_IRQ_H_ +#define __ASM_MACH_LOONGSON64_IRQ_H_ + +#include + +#define MAX_IO_PICS 2 +#define NR_IRQS (64 + (256 * MAX_IO_PICS)) + +#define CORES_PER_EIO_NODE 4 + +#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */ +#define LOONGSON_CPU_THSENS_VEC 14 /* CPU Thsens */ +#define LOONGSON_CPU_HT0_VEC 16 /* CPU HT0 irq vector base number */ +#define LOONGSON_CPU_HT1_VEC 24 /* CPU HT1 irq vector base number */ + +/* IRQ number definitions */ +#define LOONGSON_LPC_IRQ_BASE 0 +#define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15) + +#define LOONGSON_CPU_IRQ_BASE 16 +#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 14) + +#define LOONGSON_PCH_IRQ_BASE 64 +#define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47) +#define LOONGSON_PCH_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 64 - 1) + +#define LOONGSON_MSI_IRQ_BASE (LOONGSON_PCH_IRQ_BASE + 64) +#define LOONGSON_MSI_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1) + +#define GSI_MIN_LPC_IRQ LOONGSON_LPC_IRQ_BASE +#define GSI_MAX_LPC_IRQ (LOONGSON_LPC_IRQ_BASE + 16 - 1) +#define GSI_MIN_CPU_IRQ LOONGSON_CPU_IRQ_BASE +#define GSI_MAX_CPU_IRQ (LOONGSON_CPU_IRQ_BASE + 48 - 1) +#define GSI_MIN_PCH_IRQ LOONGSON_PCH_IRQ_BASE +#define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1) + +extern int find_pch_pic(u32 gsi); +extern int eiointc_get_node(int id); + +static inline void eiointc_enable(void) +{ + uint64_t misc; + + misc = iocsr_readq(LOONGARCH_IOCSR_MISC_FUNC); + misc |= IOCSR_MISC_FUNC_EXT_IOI_EN; + iocsr_writeq(misc, LOONGARCH_IOCSR_MISC_FUNC); +} + +struct acpi_madt_lio_pic; +struct acpi_madt_eio_pic; +struct acpi_madt_ht_pic; +struct acpi_madt_bio_pic; +struct acpi_madt_msi_pic; +struct acpi_madt_lpc_pic; + +struct irq_domain *liointc_acpi_init(struct irq_domain *parent, + struct acpi_madt_lio_pic *acpi_liointc); +struct irq_domain *eiointc_acpi_init(struct irq_domain *parent, + struct acpi_madt_eio_pic *acpi_eiointc); + +struct irq_domain *htvec_acpi_init(struct irq_domain *parent, + struct acpi_madt_ht_pic *acpi_htvec); +struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent, + struct acpi_madt_lpc_pic *acpi_pchlpc); +struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent, + struct acpi_madt_msi_pic *acpi_pchmsi); +struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent, + struct acpi_madt_bio_pic *acpi_pchpic); + +extern struct acpi_madt_lio_pic *acpi_liointc; +extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS]; + +extern struct acpi_madt_ht_pic *acpi_htintc; +extern struct acpi_madt_lpc_pic *acpi_pchlpc; +extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS]; +extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS]; + +extern struct irq_domain *cpu_domain; +extern struct irq_domain *liointc_domain; +extern struct irq_domain *pch_lpc_domain; +extern struct irq_domain *pch_msi_domain[MAX_IO_PICS]; +extern struct irq_domain *pch_pic_domain[MAX_IO_PICS]; + +extern void fixup_irqs(void); +extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev); + +#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/loongarch/include/asm/mach/loongson-2k.h b/arch/loongarch/include/asm/mach/loongson-2k.h new file mode 100644 index 000000000..e55bc0ea3 --- /dev/null +++ b/arch/loongarch/include/asm/mach/loongson-2k.h @@ -0,0 +1,742 @@ +/* + * Copyright (C) 2020, Loongson Technology Corporation Limited, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * +*/ + +#ifndef __ASM_MACH_LOONGSON_2K_H_ +#define __ASM_MACH_LOONGSON_2K_H_ + +#include +#include +#include +#include + +/* we need to read back to ensure the write is accepted by conf bus */ +#define CONF_BASE 0x1fe10000 + +#define CPU_WBASE0_OFF 0x0 +#define CPU_WBASE1_OFF 0x8 +#define CPU_WBASE2_OFF 0x10 +#define CPU_WBASE3_OFF 0x18 +#define CPU_WBASE4_OFF 0x20 +#define CPU_WBASE5_OFF 0x28 +#define CPU_WBASE6_OFF 0x30 +#define CPU_WBASE7_OFF 0x38 + +#define CPU_WMASK0_OFF 0x40 +#define CPU_WMASK1_OFF 0x48 +#define CPU_WMASK2_OFF 0x50 +#define CPU_WMASK3_OFF 0x58 +#define CPU_WMASK4_OFF 0x60 +#define CPU_WMASK5_OFF 0x68 +#define CPU_WMASK6_OFF 0x70 +#define CPU_WMASK7_OFF 0x78 + +#define CPU_WMMAP0_OFF 0x80 +#define CPU_WMMAP1_OFF 0x88 +#define CPU_WMMAP2_OFF 0x90 +#define CPU_WMMAP3_OFF 0x98 +#define CPU_WMMAP4_OFF 0xa0 +#define CPU_WMMAP5_OFF 0xa8 +#define CPU_WMMAP6_OFF 0xb0 +#define CPU_WMMAP7_OFF 0xb8 + +#define SCACHE_LA0_OFF 0x200 +#define SCACHE_LA1_OFF 0x208 +#define SCACHE_LA2_OFF 0x210 +#define SCACHE_LA3_OFF 0x218 + +#define SCACHE_LM0_OFF 0x240 +#define SCACHE_LM1_OFF 0x248 +#define SCACHE_LM2_OFF 0x250 +#define SCACHE_LM3_OFF 0x258 + +#define SIGNAL_OFF 0x400 + +#define GMAC_OFF 0x420 +#define UART_OFF 0x428 +#define GPU_OFF 0x430 +#define APBDMA_OFF 0x438 +#define USB_PHY01_OFF 0x440 +#define USB_PHY23_OFF 0x448 +#define SATA_OFF 0x450 +#define SATA_PHY_OFF 0x458 +#define MON_WRDMA_OFF 0x460 + +/* + * about clk manager (PLL) + */ +#if defined(CONFIG_LOONGSON_2K500) +#define PLL_NODE_0_OFFSET 0x0 +#define PLL_NODE_1_OFFSET 0x4 +#define PLL_DDR_0_OFFSET 0x8 +#define PLL_DDR_1_OFFSET 0xc +#define PLL_SOC_0_OFFSET 0x10 +#define PLL_SOC_1_OFFSET 0x14 +#define PLL_PIX0_0_OFFSET 0x18 +#define PLL_PIX0_1_OFFSET 0x1c +#define PLL_PIX1_0_OFFSET 0x20 +#define PLL_PIX1_1_OFFSET 0x24 +#define PLL_FREQ_SC 0x28 +#elif defined(CONFIG_LOONGSON_2K1000) +#define PLL_SYS0_OFF 0x480 +#define PLL_SYS1_OFF 0x488 +#define PLL_DLL0_OFF 0x490 +#define PLL_DLL1_OFF 0x498 +#define PLL_DC0_OFF 0x4a0 +#define PLL_DC1_OFF 0x4a8 +#define PLL_PIX00_OFF 0x4b0 +#define PLL_PIX01_OFF 0x4b8 +#define PLL_PIX10_OFF 0x4c0 +#define PLL_PIX11_OFF 0x4c8 +#define PLL_FREQ_SC 0x4d0 +#endif + +//6 bit [29:24] odiv +#define PLL_GENERIC_0_ODIV_SHIFT 24 +#define PLL_GENERIC_0_ODIV_MASK 0x3f + +//8 bit [23:16] loopc +#define PLL_GENERIC_0_LOOPC_SHIFT 16 +#define PLL_GENERIC_0_LOOPC_MASK 0xff + +//6 bit [13:8] refc +#define PLL_GENERIC_0_REFC_SHIFT 8 +#define PLL_GENERIC_0_REFC_MASK 0x3f + +//6 bit [13:8] +#define PLL_GENERIC_1_ODIV_1_SHIFT 8 +#define PLL_GENERIC_1_ODIV_1_MASK 0x3f + +//6 bit [5:0] +#define PLL_GENERIC_1_ODIV_0_SHIFT 0 +#define PLL_GENERIC_1_ODIV_0_MASK 0x3f + +//////////////////////////////////////// + +#define PLL_NODE_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_NODE_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_NODE_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_NODE_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_NODE_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_NODE_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +#define PLL_DDR_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_DDR_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_DDR_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_DDR_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_DDR_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_DDR_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +#define PLL_DDR_1_ODIV_HDA_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT +#define PLL_DDR_1_ODIV_HDA_MASK PLL_GENERIC_1_ODIV_1_MASK + +#define PLL_DDR_1_ODIV_NET_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT +#define PLL_DDR_1_ODIV_NET_MASK PLL_GENERIC_1_ODIV_0_MASK + +#define PLL_SOC_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_SOC_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_SOC_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_SOC_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_SOC_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_SOC_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +#define PLL_SOC_1_ODIV_GMAC_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT +#define PLL_SOC_1_ODIV_GMAC_MASK PLL_GENERIC_1_ODIV_1_MASK + +#define PLL_SOC_1_ODIV_SB_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT +#define PLL_SOC_1_ODIV_SB_MASK PLL_GENERIC_1_ODIV_0_MASK + +#define PLL_PIX0_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_PIX0_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_PIX0_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_PIX0_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_PIX0_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_PIX0_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +#define PLL_PIX1_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_PIX1_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_PIX1_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_PIX1_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_PIX1_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_PIX1_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +#define PLL_FREQSCALE_LSU_SHIFT 27 +#define PLL_FREQSCALE_LSU_MASK 0x1f + +#define PLL_FREQSCALE_PRINT_SHIFT 24 +#define PLL_FREQSCALE_PRINT_MASK 0x7 + +#define PLL_FREQSCALE_APB_SHIFT 20 +#define PLL_FREQSCALE_APB_MASK 0x7 + +#define PLL_FREQSCALE_USB_SHIFT 16 +#define PLL_FREQSCALE_USB_MASK 0x7 + +#define PLL_FREQSCALE_SATA_SHIFT 12 +#define PLL_FREQSCALE_SATA_MASK 0x7 + +#define PLL_FREQSCALE_SB_SHIFT 8 +#define PLL_FREQSCALE_SB_MASK 0x7 + +#define PLL_FREQSCALE_GPU_SHIFT 4 +#define PLL_FREQSCALE_GPU_MASK 0x7 + +#define PLL_FREQSCALE_NODE_SHIFT 0 +#define PLL_FREQSCALE_NODE_MASK 0x7 +/* + * about clk manager (PLL) + */ + +#define GPIO0_OEN_OFF 0x500 +#define GPIO1_OEN_OFF 0x508 +#define GPIO0_O_OFF 0x510 +#define GPIO1_O_OFF 0x518 +#define GPIO0_I_OFF 0x520 +#define GPIO1_I_OFF 0x528 +#define GPIO0_INT_OFF 0x528 +#define GPIO1_INT_OFF 0x530 + +#define CONF_DMA0_OFF 0xc00 + +#define CONF_DMA1_OFF 0xc10 + +#define CONF_DMA2_OFF 0xc20 + +#define CONF_DMA3_OFF 0xc30 + +#define CONF_DMA4_OFF 0xc40 + +#define C0_IPISR_OFF 0x1000 +#define C0_IPIEN_OFF 0x1004 +#define C0_IPISET_OFF 0x1008 +#define C0_IPICLR_OFF 0x100c + +#define C0_MAIL0_OFF 0x1020 +#define C0_MAIL1_OFF 0x1028 +#define C0_MAIL2_OFF 0x1030 +#define C0_MAIL3_OFF 0x1038 + +#define INTSR0_OFF 0x1040 +#define INTSR1_OFF 0x1048 + +#define C1_IPISR_OFF 0x1100 +#define C1_IPIEN_OFF 0x1104 +#define C1_IPISET_OFF 0x1108 +#define C1_IPICLR_OFF 0x110c + +#define C1_MAIL0_OFF 0x1120 +#define C1_MAIL1_OFF 0x1128 +#define C1_MAIL2_OFF 0x1130 +#define C1_MAIL3_OFF 0x1138 + +#define INT_LO_OFF 0x1400 +#define INT_HI_OFF 0x1440 + +#define INT_RTEBASE_OFF 0x0 +#define INT_SR_OFF 0x20 +#define INT_EN_OFF 0x24 +#define INT_SET_OFF 0x28 +#define INT_CLR_OFF 0x2c +#define INT_PLE_OFF 0x30 +#define INT_EDG_OFF 0x34 +#define INT_BCE_OFF 0x38 +#define INT_AUTO_OFF 0x3c + +#define THSENS_INT_CTL_HI_OFF 0x1500 +#define THSENS_INT_CTL_LO_OFF 0x1508 +#define THSENS_INT_CTL_SR_CLR_OFF 0x1510 + +#define THSENS_SCAL_OFF 0x1520 + +#define W4_BASE0_OFF 0x2400 +#define W4_BASE1_OFF 0x2408 +#define W4_BASE2_OFF 0x2410 +#define W4_BASE3_OFF 0x2418 +#define W4_BASE4_OFF 0x2420 +#define W4_BASE5_OFF 0x2428 +#define W4_BASE6_OFF 0x2430 +#define W4_BASE7_OFF 0x2438 + +#define W4_MASK0_OFF 0x2440 +#define W4_MASK1_OFF 0x2448 +#define W4_MASK2_OFF 0x2450 +#define W4_MASK3_OFF 0x2458 +#define W4_MASK4_OFF 0x2460 +#define W4_MASK5_OFF 0x2468 +#define W4_MASK6_OFF 0x2470 +#define W4_MASK7_OFF 0x2478 + +#define W4_MMAP0_OFF 0x2480 +#define W4_MMAP1_OFF 0x2488 +#define W4_MMAP2_OFF 0x2490 +#define W4_MMAP3_OFF 0x2498 +#define W4_MMAP4_OFF 0x24a0 +#define W4_MMAP5_OFF 0x24a8 +#define W4_MMAP6_OFF 0x24b0 +#define W4_MMAP7_OFF 0x24b8 + +#define w5_BASE0_OFF 0x2500 +#define w5_BASE1_OFF 0x2508 +#define w5_BASE2_OFF 0x2510 +#define w5_BASE3_OFF 0x2518 +#define w5_BASE4_OFF 0x2520 +#define w5_BASE5_OFF 0x2528 +#define w5_BASE6_OFF 0x2530 +#define w5_BASE7_OFF 0x2538 + +#define w5_MASK0_OFF 0x2540 +#define w5_MASK1_OFF 0x2548 +#define w5_MASK2_OFF 0x2550 +#define w5_MASK3_OFF 0x2558 +#define w5_MASK4_OFF 0x2560 +#define w5_MASK5_OFF 0x2568 +#define w5_MASK6_OFF 0x2570 +#define w5_MASK7_OFF 0x2578 + +#define w5_MMAP0_OFF 0x2580 +#define w5_MMAP1_OFF 0x2588 +#define w5_MMAP2_OFF 0x2590 +#define w5_MMAP3_OFF 0x2598 +#define w5_MMAP4_OFF 0x25a0 +#define w5_MMAP5_OFF 0x25a8 +#define w5_MMAP6_OFF 0x25b0 +#define w5_MMAP7_OFF 0x25b8 + +#define PCI_HEAD20_OFF 0x3000 + +#define PCI_HEAD30_OFF 0x3040 + +#define PCI_HEAD31_OFF 0x3080 + +#define PCI_HEAD40_OFF 0x30c0 + +#define PCI_HEAD41_OFF 0x3100 + +#define PCI_HEAD42_OFF 0x3140 + +#define PCI_HEAD50_OFF 0x3180 + +#define PCI_HEAD60_OFF 0x31c0 + +#define PCI_HEAD70_OFF 0x3200 + +#define PCI_HEAD80_OFF 0x3240 + +#define PCI_HEADF0_OFF 0x32c0 + +#define PCI_CFG20_OFF 0x3800 +#define PCI_CFG30_OFF 0x3808 +#define PCI_CFG31_OFF 0x3810 +#define PCI_CFG40_OFF 0x3818 +#define PCI_CFG41_OFF 0x3820 +#define PCI_CFG42_OFF 0x3828 +#define PCI_CFG50_OFF 0x3830 +#define PCI_CFG60_OFF 0x3838 +#define PCI_CFG70_OFF 0x3840 +#define PCI_CFG80_OFF 0x3848 +#define PCI_CFGF0_OFF 0x3850 + +#define CHIP_ID_OFF 0x3ff8 +/* end of conf bus */ + +#if defined(CONFIG_LOONGSON_2K500) +#define APB_BASE 0x1ff00000 +#elif defined(CONFIG_LOONGSON_2K1000) +#define APB_BASE 0x1fe00000 +#endif + +#define UART0_OFF 0x0 +#define UART1_OFF 0x100 +#define UART2_OFF 0x200 +#define UART3_OFF 0x300 +#define UART4_OFF 0x400 +#define UART5_OFF 0x500 +#define UART6_OFF 0x600 +#define UART7_OFF 0x700 +#define UART8_OFF 0x800 +#define UART9_OFF 0x900 +#define UARTA_OFF 0xa00 +#define UARTB_OFF 0xb00 + +#define I2C0_OFF 0x1000 +#define I2C1_OFF 0x1800 + +#define PWM_OFF 0x2000 + +#define HPET_OFF 0x4000 +#define AC97_OFF 0x5000 +#define NAND_OFF 0x6000 + +#define ACPI_OFF 0x7000 + +#define RTC_OFF 0x7800 + +#define DES_OFF 0x8000 +#define AES_OFF 0x9000 +#define RSA_OFF 0xa000 +#define RNG_OFF 0xb000 +#define SDIO_OFF 0xc000 +#define I2S_OFF 0xd000 + +#define IPI_BASE_OF(i) CKSEG1ADDR((CONF_BASE+0x100*i)) + +#define IPI_OFF_STATUS 0x1000 +#define IPI_OFF_ENABLE 0x1004 +#define IPI_OFF_SET 0x1008 +#define IPI_OFF_CLEAR 0x100c +#define IPI_OFF_MAILBOX0 0x1020 +#define IPI_OFF_MAILBOX1 0x1028 +#define IPI_OFF_MAILBOX2 0x1030 +#define IPI_OFF_MAILBOX3 0x1038 + +#define VRAM_TYPE_SP 0 +#define VRAM_TYPE_UMA 1 +#define VRAM_TYPE_SP 0 /*GPU use his private memory with special address space*/ +#define VRAM_TYPE_UMA_SP 1 /*GPU use his private memory with unified address space*/ +#define VRAM_TYPE_UMA_LOW 2 /*GPU use low address syetem memory with unified address space*/ +#define VRAM_TYPE_UMA_HIGH 3 /*GPU use high address syetem memory with unified address space*/ +#define VRAM_TYPE_SP_LOW 4 /*GPU use low address syetem memory with special address space*/ +#define VRAM_TYPE_SP_HIGH 5 /*GPU use high address syetem memory with special address space*/ + +#define LS2K_IO_REG_BASE 0x1f000000 + +/* CHIP CONFIG regs */ +#define LS2K_CHIP_CFG_REG_BASE (LS2K_IO_REG_BASE + 0x00e10000) +#define LS2K_APBDMA_CONFIG_REG (LS2K_CHIP_CFG_REG_BASE + 0x438) +#define LS2K_GEN_CONFIG0_REG (LS2K_CHIP_CFG_REG_BASE + 0x420) +#define LS2K_GEN_CONFIG1_REG (LS2K_CHIP_CFG_REG_BASE + 0x428) + +#define LS2K_PIX0_PLL (LS2K_CHIP_CFG_REG_BASE + 0x4b0) +#define LS2K_PIX1_PLL (LS2K_CHIP_CFG_REG_BASE + 0x4c0) + +#define LS2K_INT_REG_BASE (LS2K_CHIP_CFG_REG_BASE + 0x1420) + +#define LS2K_INT_ISR0_REG (LS2K_CHIP_CFG_REG_BASE + 0x1420) +#define LS2K_INT_IEN0_REG (LS2K_CHIP_CFG_REG_BASE + 0x1424) +#define LS2K_INT_SET0_REG (LS2K_CHIP_CFG_REG_BASE + 0x1428) +#define LS2K_INT_CLR0_REG (LS2K_CHIP_CFG_REG_BASE + 0x142c) +#define LS2K_INT_POL0_REG (LS2K_CHIP_CFG_REG_BASE + 0x1430) +#define LS2K_INT_EDGE0_REG (LS2K_CHIP_CFG_REG_BASE + 0x1434) +#define LS2K_INT_BOUNCE_REG (LS2K_CHIP_CFG_REG_BASE + 0x1438) +#define LS2K_INT_AUTO_REG (LS2K_CHIP_CFG_REG_BASE + 0x143c) + +#define LS2K_GPIO0_OEN_REG (LS2K_CHIP_CFG_REG_BASE + 0x0500) +#define LS2K_GPIO1_OEN_REG (LS2K_CHIP_CFG_REG_BASE + 0x0508) +#define LS2K_GPIO0_O_REG (LS2K_CHIP_CFG_REG_BASE + 0x0510) +#define LS2K_GPIO1_O_REG (LS2K_CHIP_CFG_REG_BASE + 0x0518) +#define LS2K_GPIO0_I_REG (LS2K_CHIP_CFG_REG_BASE + 0x0520) +#define LS2K_GPIO1_I_REG (LS2K_CHIP_CFG_REG_BASE + 0x0528) +#define LS2K_GPIO0_INT_REG (LS2K_CHIP_CFG_REG_BASE + 0x0530) +#define LS2K_GPIO1_INT_REG (LS2K_CHIP_CFG_REG_BASE + 0x0538) + +#define LS2K_DMA_ORDER_REG (LS2K_CHIP_CFG_REG_BASE + 0x0c00) +#define LS2K_CHIP_CFG0_REG (LS2K_CHIP_CFG_REG_BASE + 0x0200) +#define LS2K_CHIP_CFG1_REG (LS2K_CHIP_CFG_REG_BASE + 0x0204) +#define LS2K_CHIP_CFG2_REG (LS2K_CHIP_CFG_REG_BASE + 0x0208) +#define LS2K_CHIP_CFG3_REG (LS2K_CHIP_CFG_REG_BASE + 0x020c) +#define LS2K_CHIP_SAMP0_REG (LS2K_CHIP_CFG_REG_BASE + 0x0210) +#define LS2K_CHIP_SAMP1_REG (LS2K_CHIP_CFG_REG_BASE + 0x0214) +#define LS2K_CHIP_SAMP2_REG (LS2K_CHIP_CFG_REG_BASE + 0x0218) +#define LS2K_CHIP_SAMP3_REG (LS2K_CHIP_CFG_REG_BASE + 0x021c) +#define LS2K_CLK_CTRL0_REG (LS2K_CHIP_CFG_REG_BASE + 0x0220) +#define LS2K_CLK_CTRL1_REG (LS2K_CHIP_CFG_REG_BASE + 0x0224) +#define LS2K_CLK_CTRL2_REG (LS2K_CHIP_CFG_REG_BASE + 0x0228) +#define LS2K_CLK_CTRL3_REG (LS2K_CHIP_CFG_REG_BASE + 0x022c) +#define LS2K_PIXCLK0_CTRL0_REG (LS2K_CHIP_CFG_REG_BASE + 0x0230) +#define LS2K_PIXCLK0_CTRL1_REG (LS2K_CHIP_CFG_REG_BASE + 0x0234) +#define LS2K_PIXCLK1_CTRL0_REG (LS2K_CHIP_CFG_REG_BASE + 0x0238) +#define LS2K_PIXCLK1_CTRL1_REG (LS2K_CHIP_CFG_REG_BASE + 0x023c) + +#define LS2K_WIN_CFG_BASE (LS2K_CHIP_CFG_REG_BASE + 0x80000) +#define LS2K_M4_WIN0_BASE_REG (LS2K_WIN_CFG_BASE + 0x0400) +#define LS2K_M4_WIN0_MASK_REG (LS2K_WIN_CFG_BASE + 0x0440) +#define LS2K_M4_WIN0_MMAP_REG (LS2K_WIN_CFG_BASE + 0x0480) + +/* USB regs */ +#define LS2K_EHCI_REG_BASE (LS2K_IO_REG_BASE + 0x00e00000) +#define LS2K_OHCI_REG_BASE (LS2K_IO_REG_BASE + 0x00e08000) + +/* GMAC regs */ +#define LS2K_GMAC0_REG_BASE (LS2K_IO_REG_BASE + 0x00e10000) +#define LS2K_GMAC1_REG_BASE (LS2K_IO_REG_BASE + 0x00e18000) + +/* HDA regs */ +#define LS2K_HDA_REG_BASE (LS2K_IO_REG_BASE + 0x00e20000) + +/* SATAregs */ +#define LS2K_SATA_REG_BASE (LS2K_IO_REG_BASE + 0x00e30000) + +/* OTG regs */ +#define LS2K_OTG_REG_BASE (LS2K_IO_REG_BASE + 0x00e60000) + +/* UART regs */ +#define LS2K_UART0_REG_BASE (LS2K_IO_REG_BASE + 0x00e00000) +#define LS2K_UART1_REG_BASE (LS2K_IO_REG_BASE + 0x00e00100) +#define LS2K_UART2_REG_BASE (LS2K_IO_REG_BASE + 0x00e00200) +#define LS2K_UART3_REG_BASE (LS2K_IO_REG_BASE + 0x00e00300) +#define LS2K_UART4_REG_BASE (LS2K_IO_REG_BASE + 0x00e00400) +#define LS2K_UART5_REG_BASE (LS2K_IO_REG_BASE + 0x00e00500) +#define LS2K_UART6_REG_BASE (LS2K_IO_REG_BASE + 0x00e00600) +#define LS2K_UART7_REG_BASE (LS2K_IO_REG_BASE + 0x00e00700) +#define LS2K_UART8_REG_BASE (LS2K_IO_REG_BASE + 0x00e00800) +#define LS2K_UART9_REG_BASE (LS2K_IO_REG_BASE + 0x00e00900) +#define LS2K_UART10_REG_BASE (LS2K_IO_REG_BASE + 0x00e00a00) +#define LS2K_UART11_REG_BASE (LS2K_IO_REG_BASE + 0x00e00b00) + +#define LS2K_CAN0_REG_BASE (LS2K_IO_REG_BASE + 0x00e00c00) +#define LS2K_CAN1_REG_BASE (LS2K_IO_REG_BASE + 0x00e00d00) + +/* I2C regs */ +#define LS2K_I2C0_REG_BASE (LS2K_IO_REG_BASE + 0x00e01000) +#define LS2K_I2C0_PRER_LO_REG (LS2K_I2C0_REG_BASE + 0x0) +#define LS2K_I2C0_PRER_HI_REG (LS2K_I2C0_REG_BASE + 0x1) +#define LS2K_I2C0_CTR_REG (LS2K_I2C0_REG_BASE + 0x2) +#define LS2K_I2C0_TXR_REG (LS2K_I2C0_REG_BASE + 0x3) +#define LS2K_I2C0_RXR_REG (LS2K_I2C0_REG_BASE + 0x3) +#define LS2K_I2C0_CR_REG (LS2K_I2C0_REG_BASE + 0x4) +#define LS2K_I2C0_SR_REG (LS2K_I2C0_REG_BASE + 0x4) + +#define LS2K_I2C1_REG_BASE (LS2K_IO_REG_BASE + 0x00e01800) +#define LS2K_I2C1_PRER_LO_REG (LS2K_I2C1_REG_BASE + 0x0) +#define LS2K_I2C1_PRER_HI_REG (LS2K_I2C1_REG_BASE + 0x1) +#define LS2K_I2C1_CTR_REG (LS2K_I2C1_REG_BASE + 0x2) +#define LS2K_I2C1_TXR_REG (LS2K_I2C1_REG_BASE + 0x3) +#define LS2K_I2C1_RXR_REG (LS2K_I2C1_REG_BASE + 0x3) +#define LS2K_I2C1_CR_REG (LS2K_I2C1_REG_BASE + 0x4) +#define LS2K_I2C1_SR_REG (LS2K_I2C1_REG_BASE + 0x4) + +/* RTC regs */ +#define LS2K_RTC_REG_BASE (LS2K_IO_REG_BASE + 0x00e07800) +#define LS2K_TOY_TRIM_REG (LS2K_RTC_REG_BASE + 0x0020) +#define LS2K_TOY_WRITE0_REG (LS2K_RTC_REG_BASE + 0x0024) +#define LS2K_TOY_WRITE1_REG (LS2K_RTC_REG_BASE + 0x0028) +#define LS2K_TOY_READ0_REG (LS2K_RTC_REG_BASE + 0x002c) +#define LS2K_TOY_READ1_REG (LS2K_RTC_REG_BASE + 0x0030) +#define LS2K_TOY_MATCH0_REG (LS2K_RTC_REG_BASE + 0x0034) +#define LS2K_TOY_MATCH1_REG (LS2K_RTC_REG_BASE + 0x0038) +#define LS2K_TOY_MATCH2_REG (LS2K_RTC_REG_BASE + 0x003c) +#define LS2K_RTC_CTRL_REG (LS2K_RTC_REG_BASE + 0x0040) +#define LS2K_RTC_TRIM_REG (LS2K_RTC_REG_BASE + 0x0060) +#define LS2K_RTC_WRITE0_REG (LS2K_RTC_REG_BASE + 0x0064) +#define LS2K_RTC_READ0_REG (LS2K_RTC_REG_BASE + 0x0068) +#define LS2K_RTC_MATCH0_REG (LS2K_RTC_REG_BASE + 0x006c) +#define LS2K_RTC_MATCH1_REG (LS2K_RTC_REG_BASE + 0x0070) +#define LS2K_RTC_MATCH2_REG (LS2K_RTC_REG_BASE + 0x0074) + +#define LS2K_SDIO_REG_BASE (LS2K_IO_REG_BASE + 0x00e0c000) +#define LS2K_I2S_REG_BASE (LS2K_IO_REG_BASE + 0x00e0d000) + + +#define LS2K_IOINTC_HWIRQ_BASE 8 /* should keep consistent with dts */ +#define LS2K_INT_MSI_TRIGGER_0 (LS2K_CHIP_CFG_REG_BASE + 0x14b0) +#define LS2K_INT_MSI_TRIGGER_EN_0 (LS2K_CHIP_CFG_REG_BASE + 0x14b4) +#define LS2K_INT_MSI_TRIGGER_1 (LS2K_CHIP_CFG_REG_BASE + 0x14f0) +#define LS2K_INT_MSI_TRIGGER_EN_1 (LS2K_CHIP_CFG_REG_BASE + 0x14f4) +#define LS2K_IRQ_MASK 0xffffff3fbffff3ff + +#define LS2K_INTISR_REG(i) TO_UNCAC(0x1fe11420 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTEN_REG(i) TO_UNCAC(0x1fe11424 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTENSET_REG(i) TO_UNCAC(0x1fe11428 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTENCLR_REG(i) TO_UNCAC(0x1fe1142c | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTPOL_REG(i) TO_UNCAC(0x1fe11430 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTEDGE_REG(i) TO_UNCAC(0x1fe11434 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTBOUNCE_REG(i) TO_UNCAC(0x1fe11438 | (((i) > 31) ? 0x40 : 0)) +#define LS2K_INTAUTO_REG(i) TO_UNCAC(0x1fe1143c | (((i) > 31) ? 0x40 : 0)) +#define LS2K_COREx_INTISR0_REG(x) TO_UNCAC(0x1fe11040 + (x)*0x100) +#define LS2K_COREx_INTISR1_REG(x) TO_UNCAC(0x1fe11048 + (x)*0x100) +#define LS2K_IRQ_ROUTE_REG(i) TO_UNCAC((0x1fe11400 | (((i) > 31) ? 0x40 : 0))\ + + ((i) % 32)) +#define LS2K_IOINTC_IRQ_LINE 1 /* IP3 */ + +/* REG ACCESS*/ +#define ls2k_readb(addr) (*(volatile unsigned char *)TO_UNCAC(addr)) +#define ls2k_readw(addr) (*(volatile unsigned short *)TO_UNCAC(addr)) +#define ls2k_readl(addr) (*(volatile unsigned int *)TO_UNCAC(addr)) +#define ls2k_readq(addr) (*(volatile unsigned long *)TO_UNCAC(addr)) +#define ls2k_writeb(val, addr) (*(volatile unsigned char *)TO_UNCAC(addr) = (val)) +#define ls2k_writew(val, addr) (*(volatile unsigned short *)TO_UNCAC(addr) = (val)) +#define ls2k_writel(val, addr) (*(volatile unsigned int *)TO_UNCAC(addr) = (val)) +#define ls2k_writeq(val, addr) (*(volatile unsigned long *)TO_UNCAC(addr) = (val)) + +#define LS2K_VER3 3 + +struct ls2k_nand_plat_data { + int enable_arbiter; + u32 nr_parts; + u32 chip_ver; + struct mtd_partition *parts; + int cs; + u32 csrdy; + int chip_cap; +}; + +enum ACPI_Sx { + ACPI_S3 = 5, + ACPI_S4 = 6, + ACPI_S5 = 7, +}; + +#define ACPI_BASE (APB_BASE + ACPI_OFF) +#define S_GPMCR 0 +#define R_GPMCR 0x4 +#define RTC_GPMCR 0x8 +#define PM1_STS 0xc +#define PM1_SR 0x10 +#define PM1_CTR 0x14 +#define PM1_TIMER 0x18 +#define PM_PCTR 0x1c + +#define GPE0_STS 0x28 +#define GPE0_SR 0x2c +#define RST_CTR 0x00 +#define WD_CR 0x04 +#define WD_TIMER 0x08 + +#define THER_SCR 0x4c +#define G_RTC_1 0x50 +#define G_RTC_2 0x54 + +#define DPM_CfG 0x400 +#define DPM_STS 0x404 +#define DPM_CTR 0x408 + +#define DVFS_CFG 0x410 +#define DVFS_STS 0x414 +#define DVFS_CNT 0x418 + +#define MIN_FREQ_LEVEL 1 +#define DVFS_STS_STATUS_MASK (0x01) + +#define DVFS_CNT_START (0x01) +#define DVFS_CNT_UPDATE_EN (0x01 << 22) +#define DVFS_CNT_DIV(div) (div << 16) +#define DVFS_CNT_POL (0x01 << 2) +#define DVFS_CNT_VID_EN (0x01 << 1) +#define DVFS_CNT_POL_UP (0x01 << 3) +#define DVFS_CNT_POL_DOWN (~(0x01 << 3)) +#define DVFS_CNT_VID(vid) (vid << 4) + +#define DVFS_CFG_DVFS_EN (0x01) +#define DVFS_CFG_BACKUP_CLOCK (0x01 << 4) +#define DVFS_CFG_PROTECT_FULL (0x03 << 6) + +#define DVFS_STS_FEQ_STS_OFFSET 16 +#define DVFS_STS_FEQ_STS_MASK GENMASK(21, 16) + +/* ACPI ACCESS */ +#define acpi_readb(offset) ls2k_readb((ACPI_BASE + offset)) +#define acpi_readw(offset) ls2k_readw((ACPI_BASE + offset)) +#define acpi_readl(offset) ls2k_readl((ACPI_BASE + offset)) +#define acpi_readq(offset) ls2k_readq((ACPI_BASE + offset)) +#define acpi_writeb(val, offset) ls2k_writeb((val), (ACPI_BASE + offset)) +#define acpi_writew(val, offset) ls2k_writew((val), (ACPI_BASE + offset)) +#define acpi_writel(val, offset) ls2k_writel((val), (ACPI_BASE + offset)) +#define acpi_writeq(val, offset) ls2k_writeq((val), (ACPI_BASE + offset)) + + +/*clk */ +#define NODE_L2DIV_OUT_SHIFT 0 +#define NODE_L1DIV_OUT_SHIFT 42 +#define NODE_L1DIV_LOOPC_SHIFT 32 +#define NODE_L1DIV_REF_SHIFT 26 + +#define NODE_L2DIV_OUT_WIDTH 6 +#define NODE_L1DIV_OUT_WIDTH 6 +#define NODE_L1DIV_LOOPC_WIDTH 10 +#define NODE_L1DIV_REF_WIDTH 6 + +#define NODE_L2DIV_OUT_MARK 0x3f +#define NODE_L1DIV_OUT_MARK 0x3f +#define NODE_L1DIV_LOOPC_MARK 0x3ff +#define NODE_L1DIV_REF_MARK 0x3f + +#define DDR_L2DIV_OUT_HDA_SHIFT 44 +#define DDR_L2DIV_OUT_GPU_SHIFT 22 +#define DDR_L2DIV_OUT_DDR_SHIFT 0 +#define DDR_L1DIV_OUT_SHIFT 42 +#define DDR_L1DIV_LOOPC_SHIFT 32 +#define DDR_L1DIV_REF_SHIFT 26 + +#define DDR_L2DIV_OUT_HDA_WIDTH 7 +#define DDR_L2DIV_OUT_GPU_WIDTH 6 +#define DDR_L2DIV_OUT_DDR_WIDTH 6 +#define DDR_L1DIV_OUT_WIDTH 6 +#define DDR_L1DIV_LOOPC_WIDTH 10 +#define DDR_L1DIV_REF_WIDTH 6 + +#define DDR_L2DIV_OUT_HDA_MARK 0x7f +#define DDR_L2DIV_OUT_GPU_MARK 0x3f +#define DDR_L2DIV_OUT_DDR_MARK 0x3f +#define DDR_L1DIV_OUT_MARK 0x3f +#define DDR_L1DIV_LOOPC_MARK 0x3ff +#define DDR_L1DIV_REF_MARK 0x3f + + +#define DC_L2DIV_OUT_GMAC_SHIFT 22 +#define DC_L2DIV_OUT_DC_SHIFT 0 +#define DC_L1DIV_OUT_SHIFT 42 +#define DC_L1DIV_LOOPC_SHIFT 32 +#define DC_L1DIV_REF_SHIFT 26 + +#define DC_L2DIV_OUT_GMAC_WIDTH 6 +#define DC_L2DIV_OUT_DC_WIDTH 6 +#define DC_L1DIV_OUT_WIDTH 6 +#define DC_L1DIV_LOOPC_WIDTH 10 +#define DC_L1DIV_REF_WIDTH 6 + +#define DC_L2DIV_OUT_GMAC_MARK 0x3f +#define DC_L2DIV_OUT_DC_MARK 0x3f +#define DC_L1DIV_OUT_MARK 0x3f +#define DC_L1DIV_LOOPC_MARK 0x3ff +#define DC_L1DIV_REF_MARK 0x3f + + +#define PIX_L2DIV_OUT_PIX_SHIFT 0 +#define PIX_L1DIV_OUT_SHIFT 42 +#define PIX_L1DIV_LOOPC_SHIFT 32 +#define PIX_L1DIV_REF_SHIFT 26 + +#define PIX_L2DIV_OUT_GMAC_WIDTH 6 +#define PIX_L2DIV_OUT_DC_WIDTH 6 +#define PIX_L1DIV_OUT_WIDTH 6 +#define PIX_L1DIV_LOOPC_WIDTH 10 +#define PIX_L1DIV_REF_WIDTH 6 + +#define PIX_L2DIV_OUT_PIX0_MARK 0x3f +#define PIX_L1DIV_OUT_MARK 0x3f +#define PIX_L1DIV_LOOPC_MARK 0x3ff +#define PIX_L1DIV_REF_MARK 0x3f + +#define FREQSCALE_APB_SHIFT 20 +#define FREQSCALE_USB_SHIFT 16 +#define FREQSCALE_SATA_SHIFT 12 +#define FREQSCALE_BOOT_SHIFT 8 +#define FREQSCALE_NODE_SHIFT 0 + +#define FREQSCALE_APB_MARK 0x7 +#define FREQSCALE_USB_MARK 0x7 +#define FREQSCALE_SATA_MARK 0x7 +#define FREQSCALE_BOOT_MARK 0x7 +#define FREQSCALE_NODE_MARK 0x7 + +#endif /* __ASM_MACH_LOONGSON_2K_H_ */ diff --git a/arch/loongarch/include/asm/mach/loongson-2k300.h b/arch/loongarch/include/asm/mach/loongson-2k300.h new file mode 100644 index 000000000..1dd91fdae --- /dev/null +++ b/arch/loongarch/include/asm/mach/loongson-2k300.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2020, Loongson Technology Corporation Limited, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * +*/ + +#ifdef CONFIG_LOONGSON_2K300 + +#ifndef __ASM_MACH_LOONGSON_2K300_H_ +#define __ASM_MACH_LOONGSON_2K300_H_ + +#define PLL_NODE_0_OFFSET 0x0 +#define PLL_NODE_1_OFFSET 0x4 +#define PLL_DDR_0_OFFSET 0x8 +#define PLL_DDR_1_OFFSET 0xc +#define PLL_PIX_0_OFFSET 0x18 +#define PLL_PIX_1_OFFSET 0x1c +#define PLL_FREQ_SC 0x20 + +//6 bit [30:24] odiv 7bit 0x111 1111 +#define PLL_GENERIC_0_ODIV_SHIFT 24 +#define PLL_GENERIC_0_ODIV_MASK 0x7f + +//8 bit [23:15] loopc 9bit 0x1 1111 1111 +#define PLL_GENERIC_0_LOOPC_SHIFT 15 +#define PLL_GENERIC_0_LOOPC_MASK 0x1ff + +//6 bit [14:8] refc 7bit 0x111 1111 +#define PLL_GENERIC_0_REFC_SHIFT 8 +#define PLL_GENERIC_0_REFC_MASK 0x3f + +//6 bit [14:8] 7bit 0x111 1111 +#define PLL_GENERIC_1_ODIV_1_SHIFT 8 +#define PLL_GENERIC_1_ODIV_1_MASK 0x7f + +//6 bit [6:0] 7bit 0x111 1111 +#define PLL_GENERIC_1_ODIV_0_SHIFT 0 +#define PLL_GENERIC_1_ODIV_0_MASK 0x7f + +//////////////////////////////////////// + +// node and cpu +#define PLL_NODE_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_NODE_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_NODE_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_NODE_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_NODE_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_NODE_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +// i2s and gmac +#define PLL_NODE_1_ODIV_I2S_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT +#define PLL_NODE_1_ODIV_I2S_MASK PLL_GENERIC_1_ODIV_1_MASK + +#define PLL_NODE_1_ODIV_GMAC_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT +#define PLL_NODE_1_ODIV_GMAC_MASK PLL_GENERIC_1_ODIV_0_MASK + +// ddr pll and ddr +#define PLL_DDR_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_DDR_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_DDR_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_DDR_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_DDR_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_DDR_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +// devs and network +#define PLL_DDR_1_ODIV_DEVS_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT +#define PLL_DDR_1_ODIV_DEVS_MASK PLL_GENERIC_1_ODIV_1_MASK + +#define PLL_DDR_1_ODIV_NET_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT +#define PLL_DDR_1_ODIV_NET_MASK PLL_GENERIC_1_ODIV_0_MASK + +// pix pll and pix +#define PLL_PIX0_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT +#define PLL_PIX0_0_REFC_MASK PLL_GENERIC_0_REFC_MASK + +#define PLL_PIX0_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT +#define PLL_PIX0_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK + +#define PLL_PIX0_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT +#define PLL_PIX0_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK + +// gmac bp +#define PLL_PIX0_1_ODIV_GMACBP_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT +#define PLL_PIX0_1_ODIV_GMACBP_MASK PLL_GENERIC_1_ODIV_0_MASK + +#define PLL_FREQSCALE_SDIO_SHIFT 24 +#define PLL_FREQSCALE_SDIO_MASK 0xf + +#define PLL_FREQSCALE_I2S_SHIFT 20 +#define PLL_FREQSCALE_I2S_MASK 0xf + +#define PLL_FREQSCALE_APB_SHIFT 16 +#define PLL_FREQSCALE_APB_MASK 0xf + +#define PLL_FREQSCALE_USB_SHIFT 12 +#define PLL_FREQSCALE_USB_MASK 0xf + +#define PLL_FREQSCALE_BOOT_SHIFT 8 +#define PLL_FREQSCALE_BOOT_MASK 0xf + +#define PLL_FREQSCALE_PIX_SHIFT 4 +#define PLL_FREQSCALE_PIX_MASK 0xf + +#define PLL_FREQSCALE_NODE_SHIFT 0 +#define PLL_FREQSCALE_NODE_MASK 0xf +/* + * about clk manager (PLL) + */ + +#endif /* __ASM_MACH_LOONGSON_2K300_H_ */ +#endif /* CONFIG_LOONGSON_2K300 */ diff --git a/arch/loongarch/include/asm/mach/loongson.h b/arch/loongarch/include/asm/mach/loongson.h new file mode 100644 index 000000000..51b846ecf --- /dev/null +++ b/arch/loongarch/include/asm/mach/loongson.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Author: Huacai Chen + * Copyright (C) 2020 Loongson Technology Corporation Limited + */ + +#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H +#define __ASM_MACH_LOONGSON64_LOONGSON_H + +#include +#include +#include +#include +#include + +#include + +extern const struct plat_smp_ops loongson3_smp_ops; + +/* loongson-specific command line, env and memory initialization */ +extern void __init fw_init_environ(void); +extern void __init fw_init_memory(void); +extern void __init fw_init_numa_memory(void); + +#define LOONGSON_REG(x) \ + (*(volatile u32 *)((char *)TO_UNCAC(LOONGSON_REG_BASE) + (x))) + +#define LOONGSON_LIO_BASE 0x18000000 +#define LOONGSON_LIO_SIZE 0x00100000 /* 1M */ +#define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1) + +#define LOONGSON_BOOT_BASE 0x1c000000 +#define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */ +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) + +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REG_SIZE 0x00100000 /* 1M */ +#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) + +/* GPIO Regs - r/w */ + +#define LOONGSON_GPIODATA LOONGSON_REG(0x11c) +#define LOONGSON_GPIOIE LOONGSON_REG(0x120) +#define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c) + +#define MAX_PACKAGES 16 + +/* Chip Config registor of each physical cpu package */ +extern u64 loongson_chipcfg[MAX_PACKAGES]; +#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) + +/* Chip Temperature registor of each physical cpu package */ +extern u64 loongson_chiptemp[MAX_PACKAGES]; +#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) + +/* Freq Control register of each physical cpu package */ +extern u64 loongson_freqctrl[MAX_PACKAGES]; +#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) + +#define xconf_readl(addr) readl(addr) +#define xconf_readq(addr) readq(addr) + +static inline void xconf_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile ( + " st.w %[v], %[hw], 0 \n" + " ld.b $r0, %[hw], 0 \n" + : + : [hw] "r" (addr), [v] "r" (val) + ); +} + +static inline void xconf_writeq(u64 val64, volatile void __iomem *addr) +{ + asm volatile ( + " st.d %[v], %[hw], 0 \n" + " ld.b $r0, %[hw], 0 \n" + : + : [hw] "r" (addr), [v] "r" (val64) + ); +} + +/* ============== LS7A registers =============== */ +#define LS7A_PCH_REG_BASE 0x10000000UL +/* LPC regs */ +#define LS7A_LPC_REG_BASE (LS7A_PCH_REG_BASE + 0x00002000) +/* CHIPCFG regs */ +#define LS7A_CHIPCFG_REG_BASE (LS7A_PCH_REG_BASE + 0x00010000) +/* MISC reg base */ +#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000) +/* ACPI regs */ +#define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000) +/* RTC regs */ +#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100) + +#define LS7A_DMA_CFG (volatile void *)TO_UNCAC(LS7A_CHIPCFG_REG_BASE + 0x041c) +#define LS7A_DMA_NODE_SHF 8 +#define LS7A_DMA_NODE_MASK 0x1F00 + +#define LS7A_INT_MASK_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x020) +#define LS7A_INT_EDGE_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x060) +#define LS7A_INT_CLEAR_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x080) +#define LS7A_INT_HTMSI_EN_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x040) +#define LS7A_INT_ROUTE_ENTRY_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x100) +#define LS7A_INT_HTMSI_VEC_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x200) +#define LS7A_INT_STATUS_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x3a0) +#define LS7A_INT_POL_REG (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x3e0) +#define LS7A_LPC_INT_CTL (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x2000) +#define LS7A_LPC_INT_ENA (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x2004) +#define LS7A_LPC_INT_STS (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x2008) +#define LS7A_LPC_INT_CLR (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x200c) +#define LS7A_LPC_INT_POL (volatile void *)TO_UNCAC(LS7A_PCH_REG_BASE + 0x2010) + +#define LS7A_PMCON_SOC_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x000) +#define LS7A_PMCON_RESUME_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x004) +#define LS7A_PMCON_RTC_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x008) +#define LS7A_PM1_EVT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x00c) +#define LS7A_PM1_ENA_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x010) +#define LS7A_PM1_CNT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x014) +#define LS7A_PM1_TMR_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x018) +#define LS7A_P_CNT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x01c) +#define LS7A_GPE0_STS_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x028) +#define LS7A_GPE0_ENA_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x02c) +#define LS7A_RST_CNT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x030) +#define LS7A_WD_SET_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x034) +#define LS7A_WD_TIMER_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x038) +#define LS7A_THSENS_CNT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x04c) +#define LS7A_GEN_RTC_1_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x050) +#define LS7A_GEN_RTC_2_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x054) +#define LS7A_DPM_CFG_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x400) +#define LS7A_DPM_STS_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x404) +#define LS7A_DPM_CNT_REG (volatile void *)TO_UNCAC(LS7A_ACPI_REG_BASE + 0x408) + +typedef enum { + ACPI_PCI_HOTPLUG_STATUS = 1 << 1, + ACPI_CPU_HOTPLUG_STATUS = 1 << 2, + ACPI_MEM_HOTPLUG_STATUS = 1 << 3, + ACPI_POWERBUTTON_STATUS = 1 << 8, + ACPI_RTC_WAKE_STATUS = 1 << 10, + ACPI_PCI_WAKE_STATUS = 1 << 14, + ACPI_ANY_WAKE_STATUS = 1 << 15, +} AcpiEventStatusBits; + +#define HT1LO_OFFSET 0xe0000000000UL + +/* PCI Configration Space Base */ +#define MCFG_EXT_PCICFG_BASE 0xefe00000000UL + +/* REG ACCESS*/ +#define ls7a_readb(addr) (*(volatile unsigned char *)TO_UNCAC(addr)) +#define ls7a_readw(addr) (*(volatile unsigned short *)TO_UNCAC(addr)) +#define ls7a_readl(addr) (*(volatile unsigned int *)TO_UNCAC(addr)) +#define ls7a_readq(addr) (*(volatile unsigned long *)TO_UNCAC(addr)) +#define ls7a_writeb(val, addr) *(volatile unsigned char *)TO_UNCAC(addr) = (val) +#define ls7a_writew(val, addr) *(volatile unsigned short *)TO_UNCAC(addr) = (val) +#define ls7a_writel(val, addr) ls7a_write_type(val, addr, uint32_t) +#define ls7a_writeq(val, addr) ls7a_write_type(val, addr, uint64_t) +#define ls7a_write(val, addr) ls7a_write_type(val, addr, uint64_t) + +void enable_gpe_wakeup(void); +void enable_pci_wakeup(void); + +#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */ diff --git a/arch/loongarch/include/asm/mach/topology.h b/arch/loongarch/include/asm/mach/topology.h new file mode 100644 index 000000000..2bfad6a6c --- /dev/null +++ b/arch/loongarch/include/asm/mach/topology.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_MACH_TOPOLOGY_H +#define _ASM_MACH_TOPOLOGY_H + +#ifdef CONFIG_NUMA + +extern cpumask_t cpus_on_node[]; + +#define cpumask_of_node(node) (&cpus_on_node[node]) + +struct pci_bus; +extern int pcibus_to_node(struct pci_bus *); + +#define cpumask_of_pcibus(bus) (cpu_online_mask) + +extern unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES]; + +void numa_set_distance(int from, int to, int distance); + +#define node_distance(from, to) (__node_distances[(from)][(to)]) + +#else +#define pcibus_to_node(bus) 0 +#endif + +#endif /* _ASM_MACH_TOPOLOGY_H */