From 7d6aacdf8dac16caea7236de7e66421139761690 Mon Sep 17 00:00:00 2001 From: tao89959 <1036524114@qq.com> Date: Mon, 23 Mar 2026 17:21:59 +0800 Subject: [PATCH] net: phy: yt8531h: fix pll enable setup bug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Changelog: 修复yt8531h的pll设置失败问题 Signed-off-by: maoxiaochuan --- drivers/net/phy/motorcomm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 9581c86f8..7e8d29bd6 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1731,9 +1731,12 @@ static int yt8531_config_init(struct phy_device *phydev) if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { /* enable RXC clock when no wire plug */ + ret = ytphy_write_ext(phydev, 0xa000, 0); + ret = ytphy_modify_ext_with_lock(phydev, - YT8521_CLOCK_GATING_REG, - YT8521_CGR_RX_CLK_EN, 0); + YT8521_CLOCK_GATING_REG, + (1 << 12 | 0x1 << 1 | 0x1 << 2 | 0xf << 4), + (0x1 << 1 | 0x1 << 2 | 0x8 << 4)); if (ret < 0) return ret; }