Merge branch 'master' into master_gt

arch/loongarch/kernel/unaligned.c

@@ -27,12 +27,60 @@ static u32 unaligned_instructions_user;
 static u32 unaligned_instructions_kernel;
 #endif
 
+static inline unsigned long read_fpr(unsigned int idx);
+static inline void write_fpr(unsigned int idx, unsigned long value);
+
+/*
+ * Temporarily enable the FPU while touching hardware FP registers.
+ * The exception entry disables EUEN, so using base FP instructions in the
+ * unaligned-access emulator would otherwise trigger an FPD exception.
+ */
+static inline unsigned long read_fpr_hw(unsigned int idx)
+{
+	unsigned long value;
+
+	preempt_disable();
+	value = read_fpr(idx);
+	preempt_enable();
+
+	return value;
+}
+
+static inline void write_fpr_hw(unsigned int idx, unsigned long value)
+{
+	preempt_disable();
+	write_fpr(idx, value);
+	preempt_enable();
+}
+
 static inline unsigned long read_fpr(unsigned int idx)
 {
 #define READ_FPR(idx, __value)		\
 	__asm__ __volatile__("movfr2gr.d %0, $f"#idx"\n\t" : "=r"(__value));
 
 	unsigned long __value;
+	unsigned int ori_euen_fpu;
+	unsigned int ori_CRMD_IE;
+
+	ori_CRMD_IE  = 0;
+	__asm__ volatile (
+		"addi.d %0, $zero, 0x0\t\n"
+		"addi.d $t2, $zero, 0x4\t\n"
+		"csrxchg %0, $t2, 0x0\t\n"
+		: "+r"(ori_CRMD_IE)
+		:
+		: "$t2"
+	);
+
+	ori_euen_fpu = 0;
+	__asm__ volatile (
+		"addi.d %0, $zero, 0x1\t\n"
+		"addi.d $t2, $zero, 0x1\t\n"
+		"csrxchg %0, $t2, 0x2\t\n"
+		: "+r"(ori_euen_fpu)
+		:
+		: "$t2"
+	);
 
 	switch (idx) {
 	case 0:
@@ -134,6 +182,21 @@ static inline unsigned long read_fpr(unsigned int idx)
 	default:
 		panic("unexpected idx '%d'", idx);
 	}
+	__asm__ volatile (
+		"addi.d $t2, $zero, 0x1\t\n"
+		"csrxchg %0, $t2, 0x2\t\n"
+		:
+		: "r"(ori_euen_fpu)
+		: "$t2"
+	);
+
+	__asm__ volatile (
+		"addi.d $t2, $zero, 0x4\t\n"
+		"csrxchg %0, $t2, 0x0\t\n"
+		:
+		: "r"(ori_CRMD_IE)
+		: "$t2"
+	);
 #undef READ_FPR
 	return __value;
 }
@@ -143,6 +206,29 @@ static inline void write_fpr(unsigned int idx, unsigned long value)
 #define WRITE_FPR(idx, value)		\
 	__asm__ __volatile__("movgr2fr.d $f"#idx", %0\n\t" :: "r"(value));
 
+	unsigned int ori_euen_fpu;
+	unsigned int ori_CRMD_IE;
+
+	ori_CRMD_IE  = 0;
+	__asm__ volatile (
+		"addi.d %0, $zero, 0x0\t\n"
+		"addi.d $t2, $zero, 0x4\t\n"
+		"csrxchg %0, $t2, 0x0\t\n"
+		: "+r"(ori_CRMD_IE)
+		:
+		: "$t2"
+	);
+
+	ori_euen_fpu = 0;
+	__asm__ volatile (
+		"addi.d %0, $zero, 0x1\t\n"
+		"addi.d $t2, $zero, 0x1\t\n"
+		"csrxchg %0, $t2, 0x2\t\n"
+		: "+r"(ori_euen_fpu)
+		:
+		: "$t2"
+	);
+
 	switch (idx) {
 	case 0:
 		WRITE_FPR(0, value);
@@ -243,6 +329,22 @@ static inline void write_fpr(unsigned int idx, unsigned long value)
 	default:
 		panic("unexpected idx '%d'", idx);
 	}
+	__asm__ volatile (
+		"addi.d $t2, $zero, 0x1\t\n"
+		"csrxchg %0, $t2, 0x2\t\n"
+		:
+		: "r"(ori_euen_fpu)
+		: "$t2"
+	);
+
+	__asm__ volatile (
+		"addi.d $t2, $zero, 0x4\t\n"
+		"csrxchg %0, $t2, 0x0\t\n"
+		:
+		: "r"(ori_CRMD_IE)
+		: "$t2"
+	);
+
 #undef WRITE_FPR
 }
 
@@ -431,7 +533,7 @@ void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned i
 			regs->regs[insn.reg3_format.rd] = value;
 		else {
 			if (is_fpu_owner())
-				write_fpr(insn.reg3_format.rd, value);
+				write_fpr_hw(insn.reg3_format.rd, value);
 			else
 				set_fpr64(&current->thread.fpu.fpr[insn.reg3_format.rd], 0, value);
 		}
@@ -441,7 +543,7 @@ void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned i
 			value = regs->regs[insn.reg3_format.rd];
 		else {
 			if (is_fpu_owner())
-				value = read_fpr(insn.reg3_format.rd);
+				value = read_fpr_hw(insn.reg3_format.rd);
 			else
 				value = get_fpr64(&current->thread.fpu.fpr[insn.reg3_format.rd], 0);
 		}

drivers/watchdog/loongson2_wdt.c

@@ -44,6 +44,7 @@ static int ls2x_wdt_set_timeout(struct watchdog_device *wdt_dev,
 	unsigned int max_hw_heartbeat = wdt_dev->max_hw_heartbeat_ms / 1000;
 	unsigned int counts;
 
+	pr_info("wdt==>max_hw_heartbeat:%d\n", max_hw_heartbeat);
 	wdt_dev->timeout = timeout;
 
 	counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat);
@@ -88,9 +89,11 @@ static int ls2x_wdt_probe(struct platform_device *pdev)
 {
 	struct ls2x_wdt_drvdata *drvdata;
 	struct watchdog_device *ls2x_wdt;
-	unsigned long clk_rate;
+	u32 clk_rate;
+	u32 max_hw_heartbeat_s;
 	struct resource *res;
 	int err;
+	struct device_node *np = pdev->dev.of_node;
 
 	drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
 	if (!drvdata)
@@ -101,6 +104,9 @@ static int ls2x_wdt_probe(struct platform_device *pdev)
 	if (IS_ERR(drvdata->base))
 		return PTR_ERR(drvdata->base);
 
+	if(!of_property_read_u32(np,"clock-frequency",&clk_rate)) {
+		drvdata->clk_rate = clk_rate;
+	}else {
 		drvdata->clk = devm_clk_get(&pdev->dev, "wdt-clk");
 		if (IS_ERR(drvdata->clk))
 			return PTR_ERR(drvdata->clk);
@@ -110,22 +116,25 @@ static int ls2x_wdt_probe(struct platform_device *pdev)
 			dev_err(&pdev->dev, "clk enable failed\n");
 			return err;
 		}
-
 		clk_rate = clk_get_rate(drvdata->clk);
 		if (!clk_rate) {
 			err = -EINVAL;
 			goto err0;
 		}
 		drvdata->clk_rate = clk_rate;
+	}
+
+	max_hw_heartbeat_s = U32_MAX / clk_rate;
 
 	ls2x_wdt = &drvdata->wdt;
 	ls2x_wdt->info = &ls2x_wdt_info;
 	ls2x_wdt->ops = &ls2x_wdt_ops;
-	ls2x_wdt->timeout = DEFAULT_HEARTBEAT;
+	ls2x_wdt->timeout = DEFAULT_HEARTBEAT >  max_hw_heartbeat_s ? max_hw_heartbeat_s : DEFAULT_HEARTBEAT;
 	ls2x_wdt->min_timeout = 1;
-	ls2x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000;
+	ls2x_wdt->max_hw_heartbeat_ms = max_hw_heartbeat_s * 1000;
 	ls2x_wdt->parent = &pdev->dev;
 
+	pr_info("wdt timeout:%ds\n", ls2x_wdt->timeout);
 	watchdog_init_timeout(ls2x_wdt, heartbeat, &pdev->dev);
 	watchdog_set_nowayout(ls2x_wdt, nowayout);
 	watchdog_set_drvdata(ls2x_wdt, drvdata);