diff --git a/arch/loongarch/boot/dts/loongson2k300.dtsi b/arch/loongarch/boot/dts/loongson2k300.dtsi index 1a2ce983d..95ccc92aa 100644 --- a/arch/loongarch/boot/dts/loongson2k300.dtsi +++ b/arch/loongarch/boot/dts/loongson2k300.dtsi @@ -889,6 +889,26 @@ /* Optional for that dr_mode = "host" or dr_mode = "peripheral" */ }; + timers1: timer@16118000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "loongson,loongson-timers"; + reg = <0 0x16118000 0 0x1000>; + interrupt-parent = <&liointc0>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clocks CLK_APB>; + clock-names = "int"; + dmas = <&dma 0 0x400>, + <&dma 1 0x400>, + <&dma 2 0x400>, + <&dma 3 0x400>, + <&dma 4 0x400>, + <&dma 5 0x400>, + <&dma 6 0x400>; + dma-names = "ch1", "ch2", "ch3", "ch4", "com", "up", "trig"; + status = "disabled"; + }; + pwm_atim: pwm@16118000{ compatible = "loongson,ls2k-pwm-atim"; reg = <0 0x16118000 0 0x1000>; @@ -900,6 +920,25 @@ clock-frequency = <200000000>; status = "disabled"; }; + + timers2: timer@16119000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "loongson,loongson-timers"; + reg = <0 0x16119000 0 0x1000>; + interrupt-parent = <&liointc0>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clocks CLK_APB>; + clock-names = "int"; + dmas = <&dma 0 0x400>, + <&dma 1 0x400>, + <&dma 2 0x400>, + <&dma 3 0x400>, + <&dma 5 0x400>, + <&dma 6 0x400>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + }; pwm_gtim: pwm@16119000{ compatible = "loongson,ls2k-pwm-gtim"; diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index f9325bcce..182cff612 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2151,6 +2151,17 @@ config MFD_STM32_TIMERS for PWM and IIO Timer. This driver allow to share the registers between the others drivers. +config MFD_LS_TIMERS + tristate "Support for LS Timers" + depends on (MACH_LOONGSON64 && OF) || COMPILE_TEST + select MFD_CORE + select REGMAP + select REGMAP_MMIO + help + Select this option to enable Loongson timers driver used + for PWM and IIO Timer. This driver allow to share the + registers between the others drivers. + config MFD_STPMIC1 tristate "Support for STPMIC1 PMIC" depends on I2C=y && OF diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 2a9f91e81..9a1a08f25 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -264,6 +264,7 @@ obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o +obj-$(CONFIG_MFD_LS_TIMERS) += loongson-timers.o obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o diff --git a/drivers/mfd/loongson-timers.c b/drivers/mfd/loongson-timers.c new file mode 100644 index 000000000..3faa4ed59 --- /dev/null +++ b/drivers/mfd/loongson-timers.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2016 + * Author: Benjamin Gaignard + * + * Copyright (C) 2025 Ilikara <3435193369@qq.com> + * Modified by: Ilikara <3435193369@qq.com> + */ + +#include +#include +#include +#include +#include + +#include + +#define LS_TIMERS_MAX_REGISTERS 0x3fc + +/* DIER register DMA enable bits */ +static const u32 loongson_timers_dier_dmaen[LS_TIMERS_MAX_DMAS] = { + TIM_DIER_CC1DE, + TIM_DIER_CC2DE, + TIM_DIER_CC3DE, + TIM_DIER_CC4DE, + TIM_DIER_UIE, + TIM_DIER_TDE, + TIM_DIER_COMDE +}; + +static void loongson_timers_dma_done(void *p) +{ + struct loongson_timers_dma *dma = p; + struct dma_tx_state state; + enum dma_status status; + + status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state); + if (status == DMA_COMPLETE) + complete(&dma->completion); +} + +/** + * loongson_timers_dma_burst_read - Read from timers registers using DMA. + * + * Read from Loongson timers registers using DMA on a single event. + * @dev: reference to loongson_timers MFD device + * @buf: DMA'able destination buffer + * @id: loongson_timers_dmas event identifier (ch[1..4], up, trig or com) + * @reg: registers start offset for DMA to read from (like CCRx for capture) + * @num_reg: number of registers to read upon each DMA request, starting @reg. + * @bursts: number of bursts to read (e.g. like two for pwm period capture) + * @tmo_ms: timeout (milliseconds) + */ +int loongson_timers_dma_burst_read(struct device *dev, u32 *buf, + enum loongson_timers_dmas id, u32 reg, + unsigned int num_reg, unsigned int bursts, + unsigned long tmo_ms) +{ + struct loongson_timers *ddata = dev_get_drvdata(dev); + unsigned long timeout = msecs_to_jiffies(tmo_ms); + struct regmap *regmap = ddata->regmap; + struct loongson_timers_dma *dma = &ddata->dma; + size_t len = num_reg * bursts * sizeof(u32); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config; + dma_cookie_t cookie; + dma_addr_t dma_buf; + long err; + int ret; + + /* Sanity check */ + if (id < LS_TIMERS_DMA_CH1 || id >= LS_TIMERS_MAX_DMAS) + return -EINVAL; + + if (!num_reg || !bursts || reg > LS_TIMERS_MAX_REGISTERS || + (reg + num_reg * sizeof(u32)) > LS_TIMERS_MAX_REGISTERS) + return -EINVAL; + + if (!dma->chans[id]) + return -ENODEV; + mutex_lock(&dma->lock); + + /* Select DMA channel in use */ + dma->chan = dma->chans[id]; + dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); + if (dma_mapping_error(dev, dma_buf)) { + ret = -ENOMEM; + goto unlock; + } + + /* Prepare DMA read from timer registers, using DMA burst mode */ + memset(&config, 0, sizeof(config)); + config.src_addr = (dma_addr_t)dma->phys_base + reg; + config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + ret = dmaengine_slave_config(dma->chan, &config); + if (ret) + goto unmap; + + desc = dmaengine_prep_dma_cyclic(dma->chan, dma_buf, len, bursts, + DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); + if (!desc) { + ret = -EBUSY; + goto unmap; + } + + desc->callback = loongson_timers_dma_done; + desc->callback_param = dma; + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) + goto dma_term; + + reinit_completion(&dma->completion); + dma_async_issue_pending(dma->chan); + + /* Clear pending flags before enabling DMA request */ + ret = regmap_write(regmap, TIM_SR, 0); + if (ret) + goto dma_term; + + ret = regmap_update_bits(regmap, TIM_DIER, loongson_timers_dier_dmaen[id], + loongson_timers_dier_dmaen[id]); + if (ret) + goto dma_term; + + err = wait_for_completion_interruptible_timeout(&dma->completion, + timeout); + if (err == 0) + ret = -ETIMEDOUT; + else if (err < 0) + ret = err; + + regmap_update_bits(regmap, TIM_DIER, loongson_timers_dier_dmaen[id], 0); + regmap_write(regmap, TIM_SR, 0); +dma_term: + dmaengine_terminate_all(dma->chan); +unmap: + dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE); +unlock: + dma->chan = NULL; + mutex_unlock(&dma->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(loongson_timers_dma_burst_read); + +static const struct regmap_config loongson_timers_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = sizeof(u32), + .max_register = LS_TIMERS_MAX_REGISTERS, +}; + +static void loongson_timers_get_arr_size(struct loongson_timers *ddata) +{ + u32 arr; + + /* Backup ARR to restore it after getting the maximum value */ + regmap_read(ddata->regmap, TIM_ARR, &arr); + + /* + * Only the available bits will be written so when readback + * we get the maximum value of auto reload register + */ + regmap_write(ddata->regmap, TIM_ARR, ~0L); + regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr); + regmap_write(ddata->regmap, TIM_ARR, arr); +} + +static int loongson_timers_dma_probe(struct device *dev, + struct loongson_timers *ddata) +{ + int i; + int ret = 0; + char name[4]; + + init_completion(&ddata->dma.completion); + mutex_init(&ddata->dma.lock); + + /* Optional DMA support: get valid DMA channel(s) or NULL */ + for (i = LS_TIMERS_DMA_CH1; i <= LS_TIMERS_DMA_CH4; i++) { + snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1); + ddata->dma.chans[i] = dma_request_chan(dev, name); + } + ddata->dma.chans[LS_TIMERS_DMA_UP] = dma_request_chan(dev, "up"); + ddata->dma.chans[LS_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig"); + ddata->dma.chans[LS_TIMERS_DMA_COM] = dma_request_chan(dev, "com"); + + for (i = LS_TIMERS_DMA_CH1; i < LS_TIMERS_MAX_DMAS; i++) { + if (IS_ERR(ddata->dma.chans[i])) { + /* Save the first error code to return */ + if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret) + ret = PTR_ERR(ddata->dma.chans[i]); + + ddata->dma.chans[i] = NULL; + } + } + + return ret; +} + +static void loongson_timers_dma_remove(struct device *dev, + struct loongson_timers *ddata) +{ + int i; + + for (i = LS_TIMERS_DMA_CH1; i < LS_TIMERS_MAX_DMAS; i++) + if (ddata->dma.chans[i]) + dma_release_channel(ddata->dma.chans[i]); +} + +static int loongson_timers_irq_probe(struct platform_device *pdev, + struct loongson_timers *ddata) +{ + int ret; + + ret = platform_get_irq_byname_optional(pdev, "global"); + if (ret < 0 && ret != -ENXIO) { + return ret; + } else if (ret != -ENXIO) { + ddata->irq[LS_TIMERS_IRQ_GLOBAL] = ret; + ddata->nr_irqs = 1; + return 0; + } + + return 0; +} + +static int loongson_timers_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct loongson_timers *ddata; + struct resource *res; + void __iomem *mmio; + int ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + /* Timer physical addr for DMA */ + ddata->dma.phys_base = res->start; + + ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio, + &loongson_timers_regmap_cfg); + if (IS_ERR(ddata->regmap)) + return PTR_ERR(ddata->regmap); + + ddata->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ddata->clk)) + return PTR_ERR(ddata->clk); + + loongson_timers_get_arr_size(ddata); + + ret = loongson_timers_irq_probe(pdev, ddata); + if (ret) + return ret; + + ret = loongson_timers_dma_probe(dev, ddata); + if (ret) { + loongson_timers_dma_remove(dev, ddata); + return ret; + } + + platform_set_drvdata(pdev, ddata); + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret) + loongson_timers_dma_remove(dev, ddata); + + return ret; +} + +static void loongson_timers_remove(struct platform_device *pdev) +{ + struct loongson_timers *ddata = platform_get_drvdata(pdev); + + /* + * Don't use devm_ here: enfore of_platform_depopulate() happens before + * DMA are released, to avoid race on DMA. + */ + of_platform_depopulate(&pdev->dev); + loongson_timers_dma_remove(&pdev->dev, ddata); +} + +static const struct of_device_id loongson_timers_of_match[] = { + { .compatible = "loongson,loongson-timers", }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, loongson_timers_of_match); + +static struct platform_driver loongson_timers_driver = { + .probe = loongson_timers_probe, + .remove_new = loongson_timers_remove, + .driver = { + .name = "loongson-timers", + .of_match_table = loongson_timers_of_match, + }, +}; +module_platform_driver(loongson_timers_driver); + +MODULE_DESCRIPTION("Loongson Timers"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/loongson-timers.h b/include/linux/mfd/loongson-timers.h new file mode 100644 index 000000000..2161c0540 --- /dev/null +++ b/include/linux/mfd/loongson-timers.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2016 + * Author: Benjamin Gaignard + * + * Copyright (C) 2025 Ilikara <3435193369@qq.com> + * Modified by: Ilikara <3435193369@qq.com> + */ + +#ifndef _LINUX_LS_GPTIMER_H_ +#define _LINUX_LS_GPTIMER_H_ + +#include +#include +#include +#include + +#define TIM_CR1 0x00 /* Control Register 1 */ +#define TIM_CR2 0x04 /* Control Register 2 */ +#define TIM_SMCR 0x08 /* Slave mode control reg */ +#define TIM_DIER 0x0C /* DMA/interrupt register */ +#define TIM_SR 0x10 /* Status register */ +#define TIM_EGR 0x14 /* Event Generation Reg */ +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_CNT 0x24 /* Counter */ +#define TIM_PSC 0x28 /* Prescaler */ +#define TIM_ARR 0x2c /* Auto-Reload Register */ +#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ +#define TIM_CCR1 TIM_CCRx(1) /* Capt/Comp Register 1 */ +#define TIM_CCR2 TIM_CCRx(2) /* Capt/Comp Register 2 */ +#define TIM_CCR3 TIM_CCRx(3) /* Capt/Comp Register 3 */ +#define TIM_CCR4 TIM_CCRx(4) /* Capt/Comp Register 4 */ +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ + +#define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_DIR BIT(4) /* Counter Direction */ +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ + +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ +#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ + +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ + +#define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */ +#define TIM_DIER_CC1IE TIM_DIER_CCxIE(1) /* CC1 Interrupt Enable */ +#define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */ +#define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */ +#define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */ +#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ +#define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */ +#define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */ +#define TIM_DIER_CC2DE TIM_DIER_CCxDE(2) /* CC2 DMA request Enable */ +#define TIM_DIER_CC3DE TIM_DIER_CCxDE(3) /* CC3 DMA request Enable */ +#define TIM_DIER_CC4DE TIM_DIER_CCxDE(4) /* CC4 DMA request Enable */ +#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ +#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ + +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ + +#define TIM_EGR_UG BIT(0) /* Update Generation */ + +// CCMR Output +#define TIM_CCMR_OCxPE(x) BIT(3 + 8 * ((x) - 1)) /* Channel Preload Enable */ +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ +#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ +#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ +#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ +// CCMR Input +#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ +#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ + +#define TIM_CCER_CCxE(x) BIT(0 + 4 * ((x) - 1)) /* Capt/Comp x out Ena (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxP(x) BIT(1 + 4 * ((x) - 1)) /* Capt/Comp x Polarity (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxNE(x) BIT(2 + 4 * ((x) - 1)) /* Capt/Comp xN out Ena (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxNP(x) BIT(3 + 4 * ((x) - 1)) /* Capt/Comp xN Polarity (x ∈ {1, .. 4}) */ +#define TIM_CCER_CC1E TIM_CCER_CCxE(1) /* Capt/Comp 1 out Ena */ +#define TIM_CCER_CC1P TIM_CCER_CCxP(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE TIM_CCER_CCxNE(1) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP TIM_CCER_CCxNP(1) /* Capt/Comp 1N Polarity */ +#define TIM_CCER_CC2E TIM_CCER_CCxE(2) /* Capt/Comp 2 out Ena */ +#define TIM_CCER_CC2P TIM_CCER_CCxP(2) /* Capt/Comp 2 Polarity */ +#define TIM_CCER_CC2NE TIM_CCER_CCxNE(2) /* Capt/Comp 2N out Ena */ +#define TIM_CCER_CC2NP TIM_CCER_CCxNP(2) /* Capt/Comp 2N Polarity */ +#define TIM_CCER_CC3E TIM_CCER_CCxE(3) /* Capt/Comp 3 out Ena */ +#define TIM_CCER_CC3P TIM_CCER_CCxP(3) /* Capt/Comp 3 Polarity */ +#define TIM_CCER_CC3NE TIM_CCER_CCxNE(3) /* Capt/Comp 3N out Ena */ +#define TIM_CCER_CC3NP TIM_CCER_CCxNP(3) /* Capt/Comp 3N Polarity */ +#define TIM_CCER_CC4E TIM_CCER_CCxE(4) /* Capt/Comp 4 out Ena */ +#define TIM_CCER_CC4P TIM_CCER_CCxP(4) /* Capt/Comp 4 Polarity */ +#define TIM_CCER_CC4NE TIM_CCER_CCxNE(4) /* Capt/Comp 4N out Ena */ +#define TIM_CCER_CC4NP TIM_CCER_CCxNP(4) /* Capt/Comp 4N Polarity */ +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) + +#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ +#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ + +#define MAX_TIM_PSC 0xFFFF +#define MAX_TIM_ICPSC 0x3 + +#define TIM_CR2_MMS_SHIFT 4 +#define TIM_CR2_MMS2_SHIFT 20 + +#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ +#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ +#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ +#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ +#define TIM_SMCR_TS_SHIFT 4 + +enum loongson_timers_dmas { + LS_TIMERS_DMA_CH1, + LS_TIMERS_DMA_CH2, + LS_TIMERS_DMA_CH3, + LS_TIMERS_DMA_CH4, + LS_TIMERS_DMA_UP, + LS_TIMERS_DMA_TRIG, + LS_TIMERS_DMA_COM, + LS_TIMERS_MAX_DMAS, +}; + +/* LOONGSON Timer may have either a unique global interrupt or 4 interrupt lines */ +enum loongson_timers_irqs { + LS_TIMERS_IRQ_GLOBAL, /* global IRQ */ + LS_TIMERS_MAX_IRQS, +}; + +/** + * struct loongson_timers_dma - LOONGSON timer DMA handling. + * @completion: end of DMA transfer completion + * @phys_base: control registers physical base address + * @lock: protect DMA access + * @chan: DMA channel in use + * @chans: DMA channels available for this timer instance + */ +struct loongson_timers_dma { + struct completion completion; + phys_addr_t phys_base; + struct mutex lock; + struct dma_chan *chan; + struct dma_chan *chans[LS_TIMERS_MAX_DMAS]; +}; + +struct loongson_timers { + struct clk *clk; + struct regmap *regmap; + u32 max_arr; + struct loongson_timers_dma dma; /* Only to be used by the parent */ + unsigned int nr_irqs; + int irq[LS_TIMERS_MAX_IRQS]; +}; + +#if IS_REACHABLE(CONFIG_MFD_LS_TIMERS) +int loongson_timers_dma_burst_read(struct device *dev, u32 *buf, + enum loongson_timers_dmas id, u32 reg, + unsigned int num_reg, unsigned int bursts, + unsigned long tmo_ms); +#else +static inline int loongson_timers_dma_burst_read(struct device *dev, u32 *buf, + enum loongson_timers_dmas id, + u32 reg, + unsigned int num_reg, + unsigned int bursts, + unsigned long tmo_ms) +{ + return -ENODEV; +} +#endif +#endif