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feat: timer pwm driver based on mfd driver
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@@ -65,7 +65,7 @@
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#define TIM_EGR_UG BIT(0) /* Update Generation */
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// CCMR Output
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#define TIM_CCMR_OCxPE(x) BIT(3 + 8 * ((x) - 1)) /* Channel Preload Enable */
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#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
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#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
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#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
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#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
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@@ -107,6 +107,7 @@
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#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
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#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
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#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
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#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
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#define MAX_TIM_PSC 0xFFFF
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#define MAX_TIM_ICPSC 0x3
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@@ -120,6 +121,9 @@
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#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */
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#define TIM_SMCR_TS_SHIFT 4
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#define TIM_BDTR_BKF_MASK 0xF
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#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
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enum loongson_timers_dmas {
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LS_TIMERS_DMA_CH1,
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LS_TIMERS_DMA_CH2,
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