mirror of
https://gitee.com/open-loongarch/linux-5.10.git
synced 2026-10-25 12:47:11 +08:00
maoxiaochuan
3904801f2b
1.Fix spidev delay-usec cannot work 2.Fix spi transfer failed when use gpio cs 3.Support EC200N-CN 4G model 4.Fix alert/critical temperature to 75/105 for 2k300 5.Enable ch341,pl2303 for 2k300_defconfig
452 lines
10 KiB
C
452 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Linumiz 2021
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*
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* max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver
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*
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* Author: Navin Sankar Velliangiri <navin@linumiz.com>
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*/
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/spi/spi.h>
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#include <asm/unaligned.h>
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/*
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* The MSB of the register value determines whether the following byte will
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* be written or read. If it is 0, read will follow and if it is 1, write
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* will follow.
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*/
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#define MAX31865_RD_WR_BIT BIT(7)
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#define MAX31865_CFG_VBIAS BIT(7)
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#define MAX31865_CFG_1SHOT BIT(5)
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#define MAX31865_3WIRE_RTD BIT(4)
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#define MAX31865_FAULT_STATUS_CLEAR BIT(1)
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#define MAX31865_FILTER_50HZ BIT(0)
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/* The MAX31865 registers */
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#define MAX31865_CFG_REG 0x00
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#define MAX31865_RTD_MSB 0x01
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#define MAX31865_FAULT_STATUS 0x07
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#define MAX31865_FAULT_OVUV BIT(2)
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#define MAX31865_CHANNEL(num) { \
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.type = IIO_TEMP, \
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.indexed = 1, \
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.channel = num, \
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.address = num, \
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.info_mask_separate = \
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BIT(IIO_CHAN_INFO_RAW), \
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.scan_index = num, \
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}
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static const char max31865_show_samp_freq[] = "50 60";
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static const struct iio_chan_spec max31865_channels[] = {
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MAX31865_CHANNEL(0),
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MAX31865_CHANNEL(1),
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MAX31865_CHANNEL(2),
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};
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struct max31865_data {
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struct spi_device *spi;
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struct mutex lock;
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bool filter_50hz;
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bool three_wire;
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u8 buf[2] ____cacheline_aligned;
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bool use_gpio_channels;
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int channel;
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u32 channel_bits;
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u32 channel_affined;
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struct gpio_desc **force_gpios;
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struct gpio_desc **in_positive_gpios;
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struct gpio_desc **in_negative_gpios;
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};
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static int max31865_parse_gpio_channels(struct device *dev, const char* con_id,
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struct gpio_desc *** gpios, u32 num)
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{
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int i;
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*gpios = devm_kcalloc(dev, num, sizeof(**gpios), GFP_KERNEL);
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for (i = 0; i < num; i++) {
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(*gpios)[i] = devm_gpiod_get_index(dev, con_id, i,
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GPIOD_OUT_LOW);
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if (IS_ERR((*gpios)[i]))
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{
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dev_err(dev, "gpio(%s) channel[%d] get fail\n",
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con_id, i);
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return PTR_ERR((*gpios)[i]);
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}
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}
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return 0;
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}
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static int number_encode_as_gpio(u32 num, struct gpio_desc ** gpios, u32 bits)
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{
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int i;
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for (i = 0; i < bits; i++) {
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gpiod_set_value(gpios[i], (num & 1));
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num = num >> 1;
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}
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return 0;
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}
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static int max31865_select_channel(struct max31865_data* data, int channel)
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{
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if (!data->use_gpio_channels || data->channel == channel)
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return 0;
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data->channel = channel;
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channel += data->channel_affined;
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number_encode_as_gpio(channel, data->force_gpios, data->channel_bits);
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number_encode_as_gpio(channel, data->in_positive_gpios, data->channel_bits);
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number_encode_as_gpio(channel, data->in_negative_gpios, data->channel_bits);
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return 0;
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}
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static int max31865_read(struct max31865_data *data, u8 reg,
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unsigned int read_size)
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{
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return spi_write_then_read(data->spi, ®, 1, data->buf, read_size);
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}
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static int max31865_write(struct max31865_data *data, size_t len)
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{
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return spi_write(data->spi, data->buf, len);
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}
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static int enable_bias(struct max31865_data *data)
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{
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u8 cfg;
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int ret;
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ret = max31865_read(data, MAX31865_CFG_REG, 1);
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if (ret)
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return ret;
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cfg = data->buf[0];
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data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
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data->buf[1] = cfg | MAX31865_CFG_VBIAS;
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return max31865_write(data, 2);
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}
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static int disable_bias(struct max31865_data *data)
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{
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u8 cfg;
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int ret;
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ret = max31865_read(data, MAX31865_CFG_REG, 1);
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if (ret)
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return ret;
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cfg = data->buf[0];
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cfg &= ~MAX31865_CFG_VBIAS;
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data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
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data->buf[1] = cfg;
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return max31865_write(data, 2);
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}
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static int max31865_rtd_read(struct max31865_data *data, int *val)
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{
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u8 reg;
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int ret;
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/* Enable BIAS to start the conversion */
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ret = enable_bias(data);
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if (ret)
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return ret;
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/* wait 10.5ms before initiating the conversion */
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msleep(11);
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ret = max31865_read(data, MAX31865_CFG_REG, 1);
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if (ret)
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return ret;
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reg = data->buf[0];
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reg |= MAX31865_CFG_1SHOT | MAX31865_FAULT_STATUS_CLEAR;
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data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
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data->buf[1] = reg;
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ret = max31865_write(data, 2);
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if (ret)
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return ret;
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if (data->filter_50hz) {
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/* 50Hz filter mode requires 62.5ms to complete */
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msleep(63);
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} else {
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/* 60Hz filter mode requires 52ms to complete */
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msleep(52);
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}
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ret = max31865_read(data, MAX31865_RTD_MSB, 2);
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if (ret)
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return ret;
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*val = get_unaligned_be16(&data->buf) >> 1;
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return disable_bias(data);
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}
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static int max31865_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct max31865_data *data = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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max31865_select_channel(data, chan->channel);
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mutex_lock(&data->lock);
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ret = max31865_rtd_read(data, val);
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mutex_unlock(&data->lock);
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if (ret)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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/* Temp. Data resolution is 0.03125 degree centigrade */
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*val = 31;
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*val2 = 250000; /* 1000 * 0.03125 */
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return IIO_VAL_INT_PLUS_MICRO;
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default:
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return -EINVAL;
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}
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}
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static int max31865_init(struct max31865_data *data)
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{
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u8 cfg;
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int ret;
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ret = max31865_read(data, MAX31865_CFG_REG, 1);
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if (ret)
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return ret;
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cfg = data->buf[0];
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if (data->three_wire)
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/* 3-wire RTD connection */
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cfg |= MAX31865_3WIRE_RTD;
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if (data->filter_50hz)
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/* 50Hz noise rejection filter */
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cfg |= MAX31865_FILTER_50HZ;
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data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
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data->buf[1] = cfg;
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return max31865_write(data, 2);
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}
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static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf)
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{
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int ret;
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bool fault;
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct max31865_data *data = iio_priv(indio_dev);
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ret = max31865_read(data, MAX31865_FAULT_STATUS, 1);
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if (ret)
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return ret;
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fault = data->buf[0] & faultbit;
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return sysfs_emit(buf, "%d\n", fault);
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}
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static ssize_t show_fault_ovuv(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return show_fault(dev, MAX31865_FAULT_OVUV, buf);
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}
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static ssize_t show_filter(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct max31865_data *data = iio_priv(indio_dev);
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return sysfs_emit(buf, "%d\n", data->filter_50hz ? 50 : 60);
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}
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static ssize_t set_filter(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct max31865_data *data = iio_priv(indio_dev);
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unsigned int freq;
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int ret;
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ret = kstrtouint(buf, 10, &freq);
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if (ret)
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return ret;
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switch (freq) {
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case 50:
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data->filter_50hz = true;
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break;
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case 60:
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data->filter_50hz = false;
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break;
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default:
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return -EINVAL;
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}
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mutex_lock(&data->lock);
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ret = max31865_init(data);
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mutex_unlock(&data->lock);
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if (ret)
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return ret;
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return len;
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}
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static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(max31865_show_samp_freq);
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static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0);
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static IIO_DEVICE_ATTR(in_filter_notch_center_frequency, 0644,
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show_filter, set_filter, 0);
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static struct attribute *max31865_attributes[] = {
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&iio_dev_attr_fault_ovuv.dev_attr.attr,
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&iio_const_attr_sampling_frequency_available.dev_attr.attr,
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&iio_dev_attr_in_filter_notch_center_frequency.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group max31865_group = {
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.attrs = max31865_attributes,
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};
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static const struct iio_info max31865_info = {
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.read_raw = max31865_read_raw,
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.attrs = &max31865_group,
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};
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static int max31865_probe(struct spi_device *spi)
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{
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const struct spi_device_id *id = spi_get_device_id(spi);
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struct iio_dev *indio_dev;
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struct max31865_data *data;
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struct gpio_desc* drdy_gpiod;
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int ret;
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
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if (!indio_dev)
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return -ENOMEM;
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data = iio_priv(indio_dev);
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data->spi = spi;
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data->filter_50hz = false;
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if (of_property_read_bool(spi->dev.of_node, "filter_50hz"))
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data->filter_50hz = true;
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mutex_init(&data->lock);
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indio_dev->info = &max31865_info;
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indio_dev->name = id->name;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = max31865_channels;
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indio_dev->num_channels = ARRAY_SIZE(max31865_channels);
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if (of_property_read_bool(spi->dev.of_node, "maxim,3-wire")) {
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/* select 3 wire */
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data->three_wire = 1;
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} else {
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/* select 2 or 4 wire */
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data->three_wire = 0;
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}
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ret = max31865_init(data);
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if (ret) {
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dev_err(&spi->dev, "error: Failed to configure max31865\n");
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return ret;
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}
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data->use_gpio_channels =
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of_property_read_bool(spi->dev.of_node, "use-gpio-channels");
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if (data->use_gpio_channels) {
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data->channel = -1;
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of_property_read_u32(spi->dev.of_node, "channel-bits",
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&data->channel_bits);
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of_property_read_u32(spi->dev.of_node, "channel-affined",
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&data->channel_affined);
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// num_channels less than (2^bits - affined)
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if (indio_dev->num_channels >
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((1 << data->channel_bits) - data->channel_affined))
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indio_dev->num_channels =
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(1 << data->channel_bits) - data->channel_affined;
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max31865_parse_gpio_channels(&spi->dev, "force",
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&data->force_gpios, data->channel_bits);
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max31865_parse_gpio_channels(&spi->dev, "in-positive",
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&data->in_positive_gpios, data->channel_bits);
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max31865_parse_gpio_channels(&spi->dev, "in-negative",
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&data->in_negative_gpios, data->channel_bits);
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}
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drdy_gpiod = devm_gpiod_get_optional(&spi->dev, "drdy", GPIOD_IN);
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if (IS_ERR_OR_NULL(drdy_gpiod))
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{
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dev_warn(&spi->dev, "DRDY GPIO not configured\n");
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}
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else
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{
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gpiod_direction_input(drdy_gpiod);
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dev_warn(&spi->dev, "DRDY GPIO[%d] Set INPUT\n", desc_to_gpio(drdy_gpiod));
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gpiod_put(drdy_gpiod);
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}
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return devm_iio_device_register(&spi->dev, indio_dev);
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}
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static const struct spi_device_id max31865_id[] = {
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{ "max31865", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, max31865_id);
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static const struct of_device_id max31865_of_match[] = {
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{ .compatible = "maxim,max31865" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, max31865_of_match);
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static struct spi_driver max31865_driver = {
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.driver = {
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.name = "max31865",
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.of_match_table = max31865_of_match,
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},
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.probe = max31865_probe,
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.id_table = max31865_id,
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};
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module_spi_driver(max31865_driver);
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MODULE_AUTHOR("Navin Sankar Velliangiri <navin@linumiz.com>");
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MODULE_DESCRIPTION("Maxim MAX31865 RTD-to-Digital Converter sensor driver");
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MODULE_LICENSE("GPL v2");
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