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88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Loongson Corporation
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*/
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/*
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* Authors:
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* Sui Jingfeng <suijingfeng@loongson.cn>
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*/
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#ifndef __LSDC_PLL_H__
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#define __LSDC_PLL_H__
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#include <drm/drm_device.h>
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/*
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* PIXEL PLL hardware structure
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*
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* refclk: reference frequency, 100 MHz from external oscillator
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* outclk: output frequency desired.
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*
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*
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* L1 Fref Fvco L2
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* refclk +-----------+ +------------------+ +---------+ outclk
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* ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
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* | +-----------+ +------------------+ +---------+ ^
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* | ^ ^ ^ |
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* | | | | |
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* | | | | |
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* | div_ref loopc div_out |
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* | |
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* +---- sel_out (bypass above software configurable clock if==1) ----+
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*
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* sel_out: PLL clock output selector.
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*
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* If sel_out == 1, it will take refclk as output directly,
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* the L1 Prescaler and the out divider is bypassed.
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*
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* If sel_out == 0, then:
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* outclk = refclk / div_ref * loopc / div_out;
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*
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* PLL hardware working requirements:
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*
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* 1) 20 MHz <= refclk / div_ref <= 40Mhz
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* 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
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*
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*/
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struct lsdc_pll_core_values {
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unsigned int div_ref;
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unsigned int loopc;
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unsigned int div_out;
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};
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struct lsdc_pll;
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struct lsdc_pixpll_funcs {
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int (*setup)(struct lsdc_pll * const this);
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bool (*compute)(struct lsdc_pll * const this, unsigned int clock,
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struct lsdc_pll_core_values *params_out);
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int (*update)(struct lsdc_pll * const this,
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struct lsdc_pll_core_values const *params_in);
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unsigned int (*get_clock_rate)(struct lsdc_pll * const this,
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struct lsdc_pll_core_values *pout);
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};
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struct lsdc_pll {
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const struct lsdc_pixpll_funcs *funcs;
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struct drm_device *ddev;
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void __iomem *mmio;
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/* PLL register offset */
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u32 reg_base;
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/* PLL register size in bytes */
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u32 reg_size;
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/* 100000kHz, fixed on all board found */
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unsigned int ref_clock;
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unsigned int index;
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};
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int lsdc_pixpll_init(struct lsdc_pll * const this,
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struct drm_device *ddev,
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unsigned int index);
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#endif
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