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134 lines
4.8 KiB
C
134 lines
4.8 KiB
C
/*
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* Header file for the Loongson APB DMA Controller driver
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*
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* Copyright (C) 2017 Loongson Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef LS_APB_DMA_H
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#define LS_APB_DMA_H
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extern int hw_coherentio;
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#define LS2K0500_APB_DMA_CONF 0x1fe10100
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#ifndef CONFIG_LOONGARCH
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/* For LoongArch, the dma_spec.args[0] is mask, dma_spec.args[1] is value */
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#define SEL_MASK_SHIFT(mask) (~(mask)) /* clear the mask */
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#define SEL_VAL(nr, sel) (nr) /* set new value */
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#else
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#define APBSEL_WIDTH 3
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#define APBSEL_MASK 0x7
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#define SEL_MASK_SHIFT(sel) (~(APBSEL_MASK << ((sel) * APBSEL_WIDTH))) /*clear sel region value*/
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#define SEL_VAL(nr, sel) ((nr) << ((sel) * APBSEL_WIDTH)) /*set nr into sel region*/
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#endif
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/**
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* struct ls_dma_chan - internal representation of an Loongson APBDMAC channel
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* @chan_common: common dmaengine channel object members
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* @device: parent device
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* @ch_regs: memory mapped register base
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* @mask: channel index in a mask
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* @per_if: peripheral interface
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* @mem_if: memory interface
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* @status: transmit status information from irq/prep* functions
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* to tasklet (use atomic operations)
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* @tasklet: bottom half to finish transaction work
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* @save_cfg: configuration register that is saved on suspend/resume cycle
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* @save_dscr: for cyclic operations, preserve next descriptor address in
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* the cyclic list on suspend/resume cycle
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* @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
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* @lock: serializes enqueue/dequeue operations to descriptors lists
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* @active_list: list of descriptors dmaengine is being running on
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* @queue: list of descriptors ready to be submitted to engine
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* @free_list: list of descriptors usable by the channel
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* @descs_allocated: records the actual size of the descriptor pool
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*/
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struct ls_dma_chan {
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struct dma_chan chan_common;
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struct at_dma *device;
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void __iomem *ch_regs;
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u8 mask;
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u8 per_if;
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u8 mem_if;
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unsigned long status;
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struct tasklet_struct tasklet;
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u32 save_cfg;
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u32 save_dscr;
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struct dma_slave_config dma_sconfig;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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unsigned int descs_allocated;
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};
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/**
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* struct ls_apbdma - internal representation of an Loongson APBDMA Controller
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* @chan_common: common dmaengine dma_device object members
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* @apbdma_devtype: identifier of DMA controller compatibility
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* @ch_regs: memory mapped register base
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* @clk: dma controller clock
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* @save_imr: interrupt mask register that is saved on suspend/resume cycle
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* @all_chan_mask: all channels availlable in a mask
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @chan: channels table to store ls_dma_chan structures
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*/
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struct ls_apbdma {
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struct dma_device dma_common;
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void __iomem *regs;
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struct clk *clk;
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u32 save_imr;
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u8 all_chan_mask;
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struct dma_pool *dma_desc_pool;
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/* THE END channels table */
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struct ls_dma_chan chan[0];
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};
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/**
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* struct ls_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @dma_sel: Order number of APB sel region(max 9)
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* @apb_dma_nr: Order number of APB DMA controller(max 4)
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* @common:Pointer to the APB DMA common platform device
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* @is_private: The device channels should be marked as private and not for
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* by the general purpose DMA channel allocator.
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of APB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per APB master
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* @sd: slave specific data. Used for configuring channels
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* @sd_count: count of slave data structures passed.
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*/
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struct ls_apbdma_platform_data {
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unsigned int nr_channels;
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unsigned int dma_sel;
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unsigned int apb_dma_nr;
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struct platform_device *common;
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bool is_private;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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unsigned short block_size;
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unsigned char nr_masters;
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unsigned char data_width[4];
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};
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static inline struct ls_dma_chan *to_ls_dma_chan(struct dma_chan *dchan)
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{
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return container_of(dchan, struct ls_dma_chan, chan_common);
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}
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#endif /* LS_APB_DMA_H */
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