294 lines
9.5 KiB
ArmAsm
294 lines
9.5 KiB
ArmAsm
/*********************************************************************
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* SEGGER Microcontroller GmbH *
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* The Embedded Experts *
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**********************************************************************
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* *
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* (c) 2014 - 2024 SEGGER Microcontroller GmbH *
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* *
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* www.segger.com Support: support@segger.com *
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* *
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**********************************************************************
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* *
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* All rights reserved. *
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* *
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* Redistribution and use in source and binary forms, with or *
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* without modification, are permitted provided that the following *
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* condition is met: *
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* *
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* - Redistributions of source code must retain the above copyright *
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* notice, this condition and the following disclaimer. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
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* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
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* DAMAGE. *
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* *
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**********************************************************************
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-------------------------- END-OF-HEADER -----------------------------
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File : stm32f10x_hd_Vectors.s
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Purpose : Exception and interrupt vectors for stm32f10x_hd devices.
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Additional information:
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Preprocessor Definitions
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__NO_EXTERNAL_INTERRUPTS
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If defined,
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the vector table will contain only the internal exceptions
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and interrupts.
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__VECTORS_IN_RAM
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If defined,
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an area of RAM, large enough to store the vector table,
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will be reserved.
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__OPTIMIZATION_SMALL
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If defined,
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all weak definitions of interrupt handlers will share the
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same implementation.
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If not defined,
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all weak definitions of interrupt handlers will be defined
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with their own implementation.
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*/
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.syntax unified
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/*********************************************************************
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*
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* Macros
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*
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**********************************************************************
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*/
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//
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// Directly place a vector (word) in the vector table
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//
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.macro VECTOR Name=
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.section .vectors, "ax"
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.code 16
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.word \Name
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.endm
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//
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// Declare an exception handler with a weak definition
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//
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.macro EXC_HANDLER Name=
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//
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// Insert vector in vector table
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//
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.section .vectors, "ax"
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.word \Name
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//
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// Insert dummy handler in init section
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//
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.section .init.\Name, "ax"
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.thumb_func
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.weak \Name
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.balign 2
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\Name:
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1: b 1b // Endless loop
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.endm
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//
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// Declare an interrupt handler with a weak definition
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//
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.macro ISR_HANDLER Name=
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//
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// Insert vector in vector table
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//
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.section .vectors, "ax"
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.word \Name
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//
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// Insert dummy handler in init section
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//
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#if defined(__OPTIMIZATION_SMALL)
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.section .init, "ax"
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.weak \Name
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.thumb_set \Name,Dummy_Handler
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#else
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.section .init.\Name, "ax"
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.thumb_func
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.weak \Name
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.balign 2
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\Name:
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1: b 1b // Endless loop
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#endif
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.endm
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//
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// Place a reserved vector in vector table
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//
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.macro ISR_RESERVED
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.section .vectors, "ax"
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.word 0
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.endm
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//
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// Place a reserved vector in vector table
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//
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.macro ISR_RESERVED_DUMMY
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.section .vectors, "ax"
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.word Dummy_Handler
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.endm
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/*********************************************************************
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*
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* Externals
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*
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**********************************************************************
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*/
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.extern __stack_end__
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.extern Reset_Handler
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.extern HardFault_Handler
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/*********************************************************************
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*
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* Global functions
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*
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**********************************************************************
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*/
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/*********************************************************************
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*
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* Setup of the vector table and weak definition of interrupt handlers
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*
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*/
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.section .vectors, "ax"
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.code 16
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.balign 256
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.global _vectors
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_vectors:
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//
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// Internal exceptions and interrupts
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//
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VECTOR __stack_end__
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VECTOR Reset_Handler
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EXC_HANDLER NMI_Handler
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VECTOR HardFault_Handler
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#ifdef __ARM_ARCH_6M__
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ISR_RESERVED
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ISR_RESERVED
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ISR_RESERVED
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#else
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EXC_HANDLER MemManage_Handler
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EXC_HANDLER BusFault_Handler
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EXC_HANDLER UsageFault_Handler
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#endif
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ISR_RESERVED
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ISR_RESERVED
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ISR_RESERVED
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ISR_RESERVED
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EXC_HANDLER SVC_Handler
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#ifdef __ARM_ARCH_6M__
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ISR_RESERVED
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#else
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EXC_HANDLER DebugMon_Handler
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#endif
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ISR_RESERVED
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EXC_HANDLER PendSV_Handler
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EXC_HANDLER SysTick_Handler
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//
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// External interrupts
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//
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#ifndef __NO_EXTERNAL_INTERRUPTS
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ISR_HANDLER WWDG_IRQHandler
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ISR_HANDLER PVD_IRQHandler
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ISR_HANDLER TAMPER_IRQHandler
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ISR_HANDLER RTC_IRQHandler
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ISR_HANDLER FLASH_IRQHandler
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ISR_HANDLER RCC_IRQHandler
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ISR_HANDLER EXTI0_IRQHandler
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ISR_HANDLER EXTI1_IRQHandler
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ISR_HANDLER EXTI2_IRQHandler
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ISR_HANDLER EXTI3_IRQHandler
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ISR_HANDLER EXTI4_IRQHandler
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ISR_HANDLER DMA1_Channel1_IRQHandler
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ISR_HANDLER DMA1_Channel2_IRQHandler
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ISR_HANDLER DMA1_Channel3_IRQHandler
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ISR_HANDLER DMA1_Channel4_IRQHandler
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ISR_HANDLER DMA1_Channel5_IRQHandler
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ISR_HANDLER DMA1_Channel6_IRQHandler
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ISR_HANDLER DMA1_Channel7_IRQHandler
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ISR_HANDLER ADC1_2_IRQHandler
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ISR_HANDLER USB_HP_CAN1_TX_IRQHandler
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ISR_HANDLER USB_LP_CAN1_RX0_IRQHandler
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ISR_HANDLER CAN1_RX1_IRQHandler
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ISR_HANDLER CAN1_SCE_IRQHandler
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ISR_HANDLER EXTI9_5_IRQHandler
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ISR_HANDLER TIM1_BRK_IRQHandler
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ISR_HANDLER TIM1_UP_IRQHandler
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ISR_HANDLER TIM1_TRG_COM_IRQHandler
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ISR_HANDLER TIM1_CC_IRQHandler
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ISR_HANDLER TIM2_IRQHandler
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ISR_HANDLER TIM3_IRQHandler
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ISR_HANDLER TIM4_IRQHandler
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ISR_HANDLER I2C1_EV_IRQHandler
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ISR_HANDLER I2C1_ER_IRQHandler
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ISR_HANDLER I2C2_EV_IRQHandler
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ISR_HANDLER I2C2_ER_IRQHandler
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ISR_HANDLER SPI1_IRQHandler
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ISR_HANDLER SPI2_IRQHandler
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ISR_HANDLER USART1_IRQHandler
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ISR_HANDLER USART2_IRQHandler
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ISR_HANDLER USART3_IRQHandler
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ISR_HANDLER EXTI15_10_IRQHandler
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ISR_HANDLER RTCAlarm_IRQHandler
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ISR_HANDLER USBWakeUp_IRQHandler
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ISR_HANDLER TIM8_BRK_IRQHandler
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ISR_HANDLER TIM8_UP_IRQHandler
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ISR_HANDLER TIM8_TRG_COM_IRQHandler
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ISR_HANDLER TIM8_CC_IRQHandler
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ISR_HANDLER ADC3_IRQHandler
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ISR_HANDLER FSMC_IRQHandler
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ISR_HANDLER SDIO_IRQHandler
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ISR_HANDLER TIM5_IRQHandler
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ISR_HANDLER SPI3_IRQHandler
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ISR_HANDLER UART4_IRQHandler
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ISR_HANDLER UART5_IRQHandler
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ISR_HANDLER TIM6_IRQHandler
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ISR_HANDLER TIM7_IRQHandler
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ISR_HANDLER DMA2_Channel1_IRQHandler
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ISR_HANDLER DMA2_Channel2_IRQHandler
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ISR_HANDLER DMA2_Channel3_IRQHandler
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ISR_HANDLER DMA2_Channel4_5_IRQHandler
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#endif
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//
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.section .vectors, "ax"
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_vectors_end:
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#ifdef __VECTORS_IN_RAM
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//
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// Reserve space with the size of the vector table
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// in the designated RAM section.
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//
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.section .vectors_ram, "ax"
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.balign 256
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.global _vectors_ram
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_vectors_ram:
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.space _vectors_end - _vectors, 0
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#endif
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/*********************************************************************
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*
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* Dummy handler to be used for reserved interrupt vectors
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* and weak implementation of interrupts.
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*
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*/
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.section .init.Dummy_Handler, "ax"
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.thumb_func
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.weak Dummy_Handler
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.balign 2
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Dummy_Handler:
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1: b 1b // Endless loop
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/*************************** End of file ****************************/
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