From 7ad7facd3282401897c4b1d71c7f094870016ade Mon Sep 17 00:00:00 2001 From: iorebuild Date: Fri, 4 Jul 2025 20:50:54 +0800 Subject: [PATCH] =?UTF-8?q?1=E3=80=81=E6=B7=BB=E5=8A=A0=E7=A7=BB=E6=A4=8D?= =?UTF-8?q?=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../keil/src/tx_initialize_low_level.s | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 ports/cortex_m3/keil/src/tx_initialize_low_level.s diff --git a/ports/cortex_m3/keil/src/tx_initialize_low_level.s b/ports/cortex_m3/keil/src/tx_initialize_low_level.s new file mode 100644 index 0000000..5f6a008 --- /dev/null +++ b/ports/cortex_m3/keil/src/tx_initialize_low_level.s @@ -0,0 +1,121 @@ + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT __initial_sp + IMPORT __Vectors + +SYSTEM_CLOCK EQU 72000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 1000) -1) + + AREA ||.text||, CODE, READONLY + +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =__initial_sp ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__Vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__Vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + + + EXPORT __tx_SVCallHandler +__tx_SVCallHandler + B __tx_SVCallHandler + + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, lr} + BX LR +; } + + EXPORT __tx_SysTickHandler + EXPORT SysTick_Handler +__tx_SysTickHandler +SysTick_Handler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} + BL _tx_timer_interrupt + POP {r0, lr} + BX LR +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + ALIGN + LTORG + END